Change in coreboot[master]: mb/intel/adlrvp_m: Enable CR50 TPM support over SPI

[Thejaswani Putta (Code Review)]

Thejaswani Putta has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/54023 )

Change subject: mb/intel/adlrvp_m: Enable CR50 TPM support over SPI
......................................................................

mb/intel/adlrvp_m: Enable CR50 TPM support over SPI

Add Kconfig options and enable TPM device in devicetree

BUG: SYSCROS-57029
TEST:Booted the image and checked the successful TPM
communication in verstage,romstage & ramstage from
Coreboot logs.

Signed-off-by: Thejaswani Puta [e-mail] 
Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/devicetree_m.cb
M src/mainboard/intel/adlrvp/early_gpio_m.c
M src/mainboard/intel/adlrvp/gpio_m.c
4 files changed, 45 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/54023/1

diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig
index ce5665c..d807a0a 100644
--- a/src/mainboard/intel/adlrvp/Kconfig
+++ b/src/mainboard/intel/adlrvp/Kconfig
@@ -19,6 +19,9 @@
    select HAVE_SPD_IN_CBFS
    select DRIVERS_SOUNDWIRE_ALC711
    select SOC_INTEL_CSE_LITE_SKU
+	select MAINBOARD_HAS_TPM2
+	select MAINBOARD_HAS_SPI_TPM_CR50
+	select SPI_TPM

config CHROMEOS
    select GBB_FLAG_FORCE_DEV_SWITCH_ON
@@ -96,4 +99,11 @@
 config UART_FOR_CONSOLE
    int
    default 0
+
+config DRIVER_TPM_SPI_BUS
+	default 0x2
+
+config TPM_TIS_ACPI_INTERRUPT
+	int
+	default 67  # GPE0_DW2_3 (GPP_E3)
 endif
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 51d97bc..1e57e10 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -4,6 +4,15 @@
    	device lapic 0 on end
    end

+	# This disables autonomous GPIO power management, otherwise
+	# old cr50 FW only supports short pulses.
+	register "gpio_override_pm" = "1"
+	register "gpio_pm[COMM_0]" = "0"
+	register "gpio_pm[COMM_1]" = "0"
+	register "gpio_pm[COMM_2]" = "0"
+	register "gpio_pm[COMM_4]" = "0"
+	register "gpio_pm[COMM_5]" = "0"
+
    # GPE configuration
    # Note that GPE events called out in ASL code rely on this
    # route. i.e. If this route changes then the affected GPE
@@ -97,14 +106,14 @@

register "SerialIoGSpiMode" = "{
    	[PchSerialIoIndexGSPI0] = PchSerialIoPci,
-		[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
    	[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
    	[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
    }"

register "SerialIoGSpiCsMode" = "{
    	[PchSerialIoIndexGSPI0] = 0,
-		[PchSerialIoIndexGSPI1] = 0,
+		[PchSerialIoIndexGSPI1] = 1,
    	[PchSerialIoIndexGSPI2] = 0,
    	[PchSerialIoIndexGSPI3] = 0,
    }"
@@ -131,6 +140,10 @@
    # Intel Common SoC Config
    register "common_soc_config" = "{
    	.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.gspi[1] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
    	.i2c[0] = {
    		.speed = I2C_SPEED_FAST,
    	},
@@ -233,7 +246,14 @@
    	device pci 1e.0 on  end # UART0
    	device pci 1e.1 off end # UART1
    	device pci 1e.2 on  end # GSPI0
-		device pci 1e.3 off end # GSPI1
+		device pci 1e.3 on
+			chip drivers/spi/acpi
+				register "hid" = "ACPI_DT_NAMESPACE_HID"
+				register "compat_string" = ""google,cr50""
+				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E3_IRQ)"
+				device spi 0 on end
+			end
+		end # GSPI1
    	device pci 1f.0 on  end # eSPI
    	device pci 1f.1 on  end # P2SB
    	device pci 1f.2 hidden  end # PMC
diff --git a/src/mainboard/intel/adlrvp/early_gpio_m.c b/src/mainboard/intel/adlrvp/early_gpio_m.c
index 116d3c6..24b8980 100644
--- a/src/mainboard/intel/adlrvp/early_gpio_m.c
+++ b/src/mainboard/intel/adlrvp/early_gpio_m.c
@@ -11,6 +11,17 @@
    PAD_CFG_GPO(GPP_E5, 0, PLTRST),
    /* WWAN_PWR_EN */
    PAD_CFG_GPO(GPP_A8, 1, DEEP),
+	/* H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
+	/* TPM */
+	/* F16 : GSPI1_CS0N */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
+	/* F11 : GSPI1_CLK */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
+	/* F13 : GSPI1_MISO */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
+	/* F12 : GSPI1_MOSI */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
 };

static const struct pad_config early_uart_gpio_table[] = {
diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c
index 6f89fd2..85d6ccf 100644
--- a/src/mainboard/intel/adlrvp/gpio_m.c
+++ b/src/mainboard/intel/adlrvp/gpio_m.c
@@ -157,7 +157,7 @@
    PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),

/* S7 : SNDW4_DATA */
-	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2)
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
 };

void variant_configure_gpio_pads(void)