York Yang (york.yang@intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10837
-gerrit
commit 481247cf121059c91a7a91c2445c799bbcabd386 Author: York Yang york.yang@intel.com Date: Tue Jul 7 10:07:51 2015 -0700
intel/fsp_baytrail: Remove PcdEnableLan option
Bay Trail SOCs do not integrate LAN controller hence Baytrail FSP has no LAN control function. Remove PcdEnableLan option from UPD_DATA_REGION structure.
Change-Id: I9b4ec9d72c8c60b928a6d9755e94203fb90b658f Signed-off-by: York Yang york.yang@intel.com --- src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h old mode 100644 new mode 100755 index b001cdb..02de3cb --- a/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h +++ b/src/vendorcode/intel/fsp1_0/baytrail/include/fspvpd.h @@ -1,6 +1,6 @@ /**
-Copyright (C) 2013-2014 Intel Corporation +Copyright (C) 2013-2015 Intel Corporation
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -67,7 +67,7 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdEnableHsuart0; /* Offset 0x0029 */ UINT8 PcdEnableHsuart1; /* Offset 0x002A */ UINT8 PcdEnableSpi; /* Offset 0x002B */ - UINT8 PcdEnableLan; /* Offset 0x002C */ + UINT8 ReservedUpdSpace1; /* Offset 0x002C */ UINT8 PcdEnableSata; /* Offset 0x002D */ UINT8 PcdSataMode; /* Offset 0x002E */ UINT8 PcdEnableAzalia; /* Offset 0x002F */
-
York Yang