Harrie Paijmans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87246?usp=email )
Change subject: soc/intel/alderlake/vr_config: Add X7433RE ......................................................................
soc/intel/alderlake/vr_config: Add X7433RE
Add the Amstonlake (9W) with MCH_ID 0x4674 to the vr_config table.
BUG=NA TEST=Boots on Intel Alderlake CRB with X7433RE processor
Change-Id: I7249d3223ccbb1671a0b84da1c2347737e1aec89 Signed-off-by: Harrie Paijmans hpaijmans@eltan.com --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/vr_config.c 2 files changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/87246/1
diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 6a95918..10f2d3c 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -83,6 +83,7 @@ ADL_S_402_35W_CORE, ADL_S_202_46W_CORE, ADL_S_202_35W_CORE, + ASL_041_9W_CORE, RPL_P_682_642_482_45W_CORE, RPL_P_682_482_282_28W_CORE, RPL_P_282_242_142_15W_CORE, @@ -185,6 +186,7 @@ { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_60W_CORE, TDP_60W }, { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W }, + { PCI_DID_INTEL_ASL_ID_2, ASL_041_9W_CORE, TDP_9W }, { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W }, diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 95dba9f..eea9c41 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -90,6 +90,20 @@ * +----------------+-----------+-------+-------+---------+-------------+----------+ */
+/* + * VR Configurations for IA and GT domains for ASL SKU's. + * Per doc#721616 ADL N ASL EDS Addendum + * + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | SKU | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | + * | | |(mOhms)|(mOhms)| (A) | (A) | (msec) | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + * | ASL 041 (9W) | IA | 5.0 | 5.0 | 32 | 12 | 28000 | + * + +-----------+-------+-------+---------+-------------+----------+ + * | | GT | 6.5 | 6.5 | 29 | 22 | 28000 | + * +----------------+-----------+-------+-------+---------+-------------+----------+ + */ + struct vr_lookup { uint16_t mchid; uint8_t tdp; @@ -134,6 +148,7 @@ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, @@ -204,6 +219,7 @@ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_ICC(37, 23) }, { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_ICC(27, 23) }, + { PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_ICC(32, 29) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_ICC(160, 55) }, @@ -274,6 +290,7 @@ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, @@ -344,6 +361,7 @@ { PCI_DID_INTEL_ADL_N_ID_7, 12, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 20) }, { PCI_DID_INTEL_ADL_N_ID_8, 6, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) }, { PCI_DID_INTEL_ADL_N_ID_9, 10, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 16) }, + { PCI_DID_INTEL_ASL_ID_2, 9, VR_CFG_ALL_DOMAINS_TDC_CURRENT(12, 22) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(33, 33) }, { PCI_DID_INTEL_RPL_P_ID_2, 45, VR_CFG_ALL_DOMAINS_TDC_CURRENT(86, 86) },
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Harrie Paijmans (Code Review)