Change in coreboot[master]: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip

[Kevin Chiu (Code Review)]

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46545 )

Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
......................................................................

mb/google/zork: update USB 2.0 controller Lane Parameter for berknip

Enhance USB 2.0 C0/C1 A0/A1 HS DC Voltage Level.

BUG=b:166398726
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. check U2 register is set correctly.

Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b
Signed-off-by: Kevin Chiu 
---
M src/mainboard/google/zork/variants/berknip/overridetree.cb
1 file changed, 48 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46545/1

diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb
index 674d557..e294168 100644
--- a/src/mainboard/google/zork/variants/berknip/overridetree.cb
+++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb
@@ -21,6 +21,54 @@
    register "telemetry_vddcr_soc_offset" = "0"

# End : OPN Performance Configuration
+	#USB 2.0 strength
+	register "usb_2_port_tune_params[0]" = "{
+		.com_pds_tune = 0x03,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x03,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0xf,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"
+
+	register "usb_2_port_tune_params[1]" = "{
+		.com_pds_tune = 0x03,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x03,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0xf,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"
+
+	register "usb_2_port_tune_params[2]" = "{
+		.com_pds_tune = 0x03,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x03,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0xf,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"
+
+	register "usb_2_port_tune_params[3]" = "{
+		.com_pds_tune = 0x03,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x03,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0xf,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"

# Enable I2C2 for trackpad, touchscreen, pen at 400kHz
    register "i2c[2]" = "{

[Kevin Chiu (Code Review)]

Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46545 )

Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
......................................................................

Patch Set 1: Code-Review-1

it looks like "TXVREFTUNE0" over 0x7 will cause USB lost.

[Paul Menzel (Code Review)]

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46545 )

Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46545/1/src/mainboard/google/zork/v... 
File src/mainboard/google/zork/variants/berknip/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/46545/1/src/mainboard/google/zork/v... 
PS1, Line 24: 	#USB 2.0 strength
Please add a space after the #.

[Kevin Chiu (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46545

to look at the new patch set (#2).

Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
......................................................................

mb/google/zork: update USB 2.0 controller Lane Parameter for berknip

Enhance USB 2.0 C0/C1 A0/A1 SI by increasing the level of "HS DC Voltage Level"
and " Disconnect Threshold Adjustment" registers.

BUG=b:166398726
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. check U2 register is set correctly.

Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b
Signed-off-by: Kevin Chiu 
---
M src/mainboard/google/zork/variants/berknip/overridetree.cb
1 file changed, 48 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46545/2

[Kevin Chiu (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46545

to look at the new patch set (#3).

Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
......................................................................

mb/google/zork: update USB 2.0 controller Lane Parameter for berknip

Enhance USB 2.0 C0/C1 A0/A1 SI by increasing the level of
"HS DC Voltage Level" and " Disconnect Threshold Adjustment" registers.

BUG=b:166398726
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. check U2 register is set correctly.

Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b
Signed-off-by: Kevin Chiu 
---
M src/mainboard/google/zork/variants/berknip/overridetree.cb
1 file changed, 48 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46545/3

[Kevin Chiu (Code Review)]

Hello build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46545

to look at the new patch set (#4).

Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
......................................................................

mb/google/zork: update USB 2.0 controller Lane Parameter for berknip

Enhance USB 2.0 C0/C1 A0/A1 SI by increasing the level of
"HS DC Voltage Level" and " Disconnect Threshold Adjustment" registers.
COMPDISTUNE0: 0x3->0x7
TXVREFTUNE0: 0x6->0xf

BUG=b:166398726
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. check U2 register is set correctly.

Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b
Signed-off-by: Kevin Chiu 
---
M src/mainboard/google/zork/variants/berknip/overridetree.cb
1 file changed, 48 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46545/4

[Kevin Chiu (Code Review)]

Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46545 )

Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/46545/1/src/mainboard/google/zork/v... 
File src/mainboard/google/zork/variants/berknip/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/46545/1/src/mainboard/google/zork/v... 
PS1, Line 24: 	#USB 2.0 strength
> Please add a space after the #.

Done

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46545 )

Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
......................................................................

Patch Set 4: Code-Review+1

did  you run an SI test with this patch applied? if so, I'll merge this, but without knowing that the SI test with this was successful, I'm not confident enough to just merge this

[Kevin Chiu (Code Review)]

Hello build bot (Jenkins), Martin Roth, Furquan Shaikh, Bhanu Prakash Maiya, Rob Barnes, Eric Peers, Aaron Durbin, Felix Held,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/46545

to look at the new patch set (#5).

Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
......................................................................

mb/google/zork: update USB 2.0 controller Lane Parameter for berknip

Enhance USB 2.0 C0/C1 A0/A1 SI by increasing the level of
"HS DC Voltage Level" and " Disconnect Threshold Adjustment" registers.
COMPDISTUNE0: 0x3->0x7
TXVREFTUNE0: 0x6->0xf

BUG=b:166398726
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. check U2 register is set correctly.
     3. U2 SI all pass

Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b
Signed-off-by: Kevin Chiu 
---
M src/mainboard/google/zork/variants/berknip/overridetree.cb
1 file changed, 48 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/46545/5

[Kevin Chiu (Code Review)]

Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46545 )

Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
......................................................................

Patch Set 5:
> Patch Set 4: Code-Review+1
>
> did  you run an SI test with this patch applied? if so, I'll merge this, but without knowing that the SI test with this was successful, I'm not confident enough to just merge this

Hi Flex,
U2 SI all pass, thanks.

[Felix Held (Code Review)]

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46545 )

Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
......................................................................

Patch Set 5: Code-Review+2

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46545 )

Change subject: mb/google/zork: update USB 2.0 controller Lane Parameter for berknip
......................................................................

mb/google/zork: update USB 2.0 controller Lane Parameter for berknip

Enhance USB 2.0 C0/C1 A0/A1 SI by increasing the level of
"HS DC Voltage Level" and " Disconnect Threshold Adjustment" registers.
COMPDISTUNE0: 0x3->0x7
TXVREFTUNE0: 0x6->0xf

BUG=b:166398726
BRANCH=zork
TEST=1. emerge-zork coreboot
     2. check U2 register is set correctly.
     3. U2 SI all pass

Change-Id: I69d942605c6d43ece0d71f67df3a5e00b998219b
Signed-off-by: Kevin Chiu 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46545
Reviewed-by: Felix Held 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/zork/variants/berknip/overridetree.cb
1 file changed, 48 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Felix Held: Looks good to me, approved

diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb
index 674d557..d97a2b5 100644
--- a/src/mainboard/google/zork/variants/berknip/overridetree.cb
+++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb
@@ -21,6 +21,54 @@
    register "telemetry_vddcr_soc_offset" = "0"

# End : OPN Performance Configuration
+	# USB 2.0 strength
+	register "usb_2_port_tune_params[0]" = "{
+		.com_pds_tune = 0x07,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x03,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0xf,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"
+
+	register "usb_2_port_tune_params[1]" = "{
+		.com_pds_tune = 0x07,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x03,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0xf,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"
+
+	register "usb_2_port_tune_params[2]" = "{
+		.com_pds_tune = 0x07,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x03,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0xf,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"
+
+	register "usb_2_port_tune_params[3]" = "{
+		.com_pds_tune = 0x07,
+		.sq_rx_tune = 0x3,
+		.tx_fsls_tune = 0x3,
+		.tx_pre_emp_amp_tune = 0x03,
+		.tx_pre_emp_pulse_tune = 0x0,
+		.tx_rise_tune = 0x1,
+		.rx_vref_tune = 0xf,
+		.tx_hsxv_tune = 0x3,
+		.tx_res_tune = 0x01,
+	}"

# Enable I2C2 for trackpad, touchscreen, pen at 400kHz
    register "i2c[2]" = "{