Change in ...coreboot[master]: soc/intel/cannonlake: SoC specific microcode update check

[Ronak Kanabar (Code Review)]

Hello Patrick Rudolph, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31492

to look at the new patch set (#3).

Change subject: soc/intel/cannonlake: SoC specific microcode update check
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soc/intel/cannonlake: SoC specific microcode update check

For CFL and WHL, Microcode is being loaded from FIT. Both
supports the PRMRR/SGX feature. If This is supported the FIT
microcode load will set the msr (0x08b) with the Patch id one
less than the id in the microcode binary. This results in
Microcode getting reloaded again in bootblock and ramstage.
Avoid the microcode reload by checking for PRMRR support.
CFL and WHL CPU die are based on KBL CPU so we need to have
this check, where CNL CPU die is not based on KBL CPU so
skip this check for CNL.

BUG=b:124126405
Signed-off-by: Ronak Kanabar

Change-Id: I3311a7413d27044f9c819179e5b0cb9a67b46955
---
M src/soc/intel/cannonlake/cpu.c
1 file changed, 33 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/31492/3