Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85715?usp=email )
Change subject: mb/starlabs/starbook: Add Meteor Lake (165H) variant ......................................................................
mb/starlabs/starbook: Add Meteor Lake (165H) variant
Tested using `edk2` from `https://github.com/starlabsltd/edk2/tree/uefipayload_vs%60: * Ubuntu 24.04 * Manjaro 24
No known issues.
https://starlabs.systems/pages/starbook-specification
Change-Id: I6621585086c58d19574841314796ed9db779036e Signed-off-by: Sean Rhodes sean@starlabs.systems Reviewed-on: https://review.coreboot.org/c/coreboot/+/85715 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Matt DeVillier matt.devillier@gmail.com --- M Documentation/mainboard/index.md A Documentation/mainboard/starlabs/starbook_mtl.md M src/mainboard/starlabs/starbook/Kconfig M src/mainboard/starlabs/starbook/Kconfig.name M src/mainboard/starlabs/starbook/dsdt.asl A src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk A src/mainboard/starlabs/starbook/variants/mtl/board.fmd A src/mainboard/starlabs/starbook/variants/mtl/data.vbt A src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb A src/mainboard/starlabs/starbook/variants/mtl/devtree.c A src/mainboard/starlabs/starbook/variants/mtl/gpio.c A src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c A src/mainboard/starlabs/starbook/variants/mtl/ramstage.c A src/mainboard/starlabs/starbook/variants/mtl/romstage.c 14 files changed, 1,158 insertions(+), 1 deletion(-)
Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 4a4d733..0009ef4 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -337,6 +337,7 @@ StarBook Mk V <starlabs/starbook_tgl.md> StarBook Mk VI <starlabs/starbook_adl.md> StarBook Mk VII (N200) <starlabs/starbook_adl_n.md> +StarBook Mk VII (165H) <starlabs/starbook_mtl.md> Byte Mk II <starlabs/byte_adl.md> StarFighter Mk I <starlabs/starfighter_rpl.md>
diff --git a/Documentation/mainboard/starlabs/starbook_mtl.md b/Documentation/mainboard/starlabs/starbook_mtl.md new file mode 100644 index 0000000..30c5733 --- /dev/null +++ b/Documentation/mainboard/starlabs/starbook_mtl.md @@ -0,0 +1,88 @@ +# StarBook Mk V + +## Specs + +- CPU (full processor specs available at https://ark.intel.com) + - Intel 165H (Meteor Lake) +- EC + - ITE IT5570E + - Backlit keyboard, with standard PS/2 keycodes and SCI hotkeys + - Battery + - USB-C PD Charger + - Suspend / resume +- GPU + - Intel® Arc® Graphics + - GOP driver is recommended, VBT is provided + - eDP 14-inch 3840x2160 LCD + - HDMI video + - USB-C DisplayPort video +- Memory + - 2 x DDR5 SODIMM +- Networking + - AX210 2230 WiFi / Bluetooth +- Sound + - Realtek ALC269-VB6 + - Internal speakers + - Internal microphone + - Combined headphone / microphone 3.5-mm jack + - HDMI audio + - USB-C DisplayPort audio +- Storage + - M.2 PCIe SSD + - RTS5129 MicroSD card reader +- USB + - 1920x1080 CCD camera + - USB 3.1 Gen 2 (left) + - USB 3.1 Gen 2 Type-A (left) + - USB 3.1 Gen 1 Type-A (right) + - USB 2.0 Type-A (right) + +## Building coreboot + +Please follow the [Star Labs build instructions](common/building.md) to build coreboot, using `config.starlabs_starbook_adl` as config file. + +### Preliminaries + +Prior to building coreboot the following files are required: +* Intel Flash Descriptor file (descriptor.bin) +* Intel Management Engine firmware (me.bin) +* ITE Embedded Controller firmware (ec.bin) + +The files listed below are optional: +- Splash screen image in Windows 3.1 BMP format (Logo.bmp) + +These files exist in the correct location in the StarLabsLtd/blobs repo on GitHub which is used in place of the standard 3rdparty/blobs repo. + +### Build + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.starlabs_starbook_mtl +make +``` + +## Flashing coreboot + +```{eval-rst} ++---------------------+------------+ +| Type | Value | ++=====================+============+ +| Socketed flash | no | ++---------------------+------------+ +| Vendor | Winbond | ++---------------------+------------+ +| Model | W25Q256JW | ++---------------------+------------+ +| Size | 32 MiB | ++---------------------+------------+ +| Package | SOIC-8 | ++---------------------+------------+ +| Internal flashing | yes | ++---------------------+------------+ +| External flashing | yes | ++---------------------+------------+ +``` + +Please see [here](common/flashing.md) for instructions on how to flash with fwupd. diff --git a/src/mainboard/starlabs/starbook/Kconfig b/src/mainboard/starlabs/starbook/Kconfig index d56a150..e5ceb08 100644 --- a/src/mainboard/starlabs/starbook/Kconfig +++ b/src/mainboard/starlabs/starbook/Kconfig @@ -101,6 +101,28 @@ select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SOC_INTEL_RAPTORLAKE
+config BOARD_STARLABS_STARBOOK_MTL + select BOARD_ROMSIZE_KB_32768 + select BOARD_STARLABS_STARBOOK_SERIES + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER + select EC_STARLABS_CHARGING_SPEED + select EC_STARLABS_KBL_LEVELS + select EC_STARLABS_LID_SWITCH + select EC_STARLABS_MAX_CHARGE + select EC_STARLABS_MERLIN + select EC_STARLABS_NEED_ITE_BIN + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select SOC_INTEL_COMMON_BLOCK_VTD + select SOC_INTEL_METEORLAKE + select SOC_INTEL_METEORLAKE_U_H + select SOC_INTEL_COMMON_BLOCK_TCSS + select SOC_INTEL_CRASHLOG + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SPI_FLASH_WINBOND + select TPM_MEASURED_BOOT + if BOARD_STARLABS_STARBOOK_SERIES
config CCD_PORT @@ -172,13 +194,14 @@ default "B6-I" if BOARD_STARLABS_STARBOOK_ADL default "B62-I" if BOARD_STARLABS_STARBOOK_RPL default "B7-N" if BOARD_STARLABS_STARBOOK_ADL_N + default "B7-U" if BOARD_STARLABS_STARBOOK_MTL
config MAINBOARD_PART_NUMBER default "LabTop Mk III" if BOARD_STARLABS_LABTOP_KBL default "LabTop Mk IV" if BOARD_STARLABS_LABTOP_CML default "StarBook Mk V" if BOARD_STARLABS_STARBOOK_TGL default "StarBook Mk VI" if BOARD_STARLABS_STARBOOK_ADL || BOARD_STARLABS_STARBOOK_RPL - default "StarBook Mk VII" if BOARD_STARLABS_STARBOOK_ADL_N + default "StarBook Mk VII" if BOARD_STARLABS_STARBOOK_ADL_N || BOARD_STARLABS_STARBOOK_MTL
config MAINBOARD_SMBIOS_PRODUCT_NAME default "LabTop" if BOARD_STARLABS_LABTOP_KBL || BOARD_STARLABS_LABTOP_CML @@ -211,5 +234,6 @@ default "adl" if BOARD_STARLABS_STARBOOK_ADL default "rpl" if BOARD_STARLABS_STARBOOK_RPL default "adl_n" if BOARD_STARLABS_STARBOOK_ADL_N + default "mtl" if BOARD_STARLABS_STARBOOK_MTL
endif diff --git a/src/mainboard/starlabs/starbook/Kconfig.name b/src/mainboard/starlabs/starbook/Kconfig.name index 3efc31d..e6bc4ce 100644 --- a/src/mainboard/starlabs/starbook/Kconfig.name +++ b/src/mainboard/starlabs/starbook/Kconfig.name @@ -19,3 +19,6 @@
config BOARD_STARLABS_STARBOOK_ADL_N bool "Star Labs StarBook Mk VII (N200)" + +config BOARD_STARLABS_STARBOOK_MTL + bool "Star Labs StarBook Mk VII (165H)" diff --git a/src/mainboard/starlabs/starbook/dsdt.asl b/src/mainboard/starlabs/starbook/dsdt.asl index 3b95098..169731c 100644 --- a/src/mainboard/starlabs/starbook/dsdt.asl +++ b/src/mainboard/starlabs/starbook/dsdt.asl @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h> +#include <soc/gpio.h> + DefinitionBlock( "dsdt.aml", "DSDT", @@ -34,6 +36,10 @@ #include <soc/intel/common/block/acpi/acpi/northbridge.asl> #include <soc/intel/alderlake/acpi/southbridge.asl> #include <soc/intel/alderlake/acpi/tcss.asl> +#elif CONFIG(SOC_INTEL_METEORLAKE) + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/meteorlake/acpi/southbridge.asl> + #include <soc/intel/meteorlake/acpi/tcss.asl> #endif #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
diff --git a/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk new file mode 100644 index 0000000..9abc069 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/Makefile.mk @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += romstage.c + +ramstage-y += devtree.c +ramstage-y += gpio.c +ramstage-y += hda_verb.c +ramstage-y += ramstage.c diff --git a/src/mainboard/starlabs/starbook/variants/mtl/board.fmd b/src/mainboard/starlabs/starbook/variants/mtl/board.fmd new file mode 100644 index 0000000..cfa4492 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/board.fmd @@ -0,0 +1,14 @@ +FLASH 0x2000000 { + SI_ALL 0x1200000 { + SI_DESC 0x4000 + SI_ME 0x80f000 + } + SI_BIOS 0xe00000 { + EC@0x0 0x20000 + RW_MRC_CACHE@0x20000 0x10000 + SMMSTORE@0x30000 0x40000 + CONSOLE@0x70000 0x20000 + FMAP@0x90000 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/starlabs/starbook/variants/mtl/data.vbt b/src/mainboard/starlabs/starbook/variants/mtl/data.vbt new file mode 100644 index 0000000..9dec888 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/data.vbt Binary files differ diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb new file mode 100644 index 0000000..fa56ef8 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/devicetree.cb @@ -0,0 +1,265 @@ +chip soc/intel/meteorlake + # FSP UPDs + register "eist_enable" = "true" + register "sagv" = "SAGV_ENABLED" + + # Serial I/O + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + }" + + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + }" + + register "pmc_gpe0_dw0" = "PMC_GPP_F" + register "pmc_gpe0_dw1" = "PMC_GPP_C" + register "pmc_gpe0_dw2" = "PMC_GPP_E" + + # Device Tree + device domain 0 on + device ref igpu on + register "gfx" = "GMA_DEFAULT_PANEL(0)" + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_2] = DDI_ENABLE_HPD, + }" + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref tcss_usb3_port2 on end + end + end + end + end + device ref gna on end + device ref xhci on + # Motherboard USB 3.0 Type-C Front 9557 mil + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + # Motherboard USB 3.0 Type-C Back 7893 mil + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + # Motherboard USB 3.0 Type-A 8916 mil + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Daughterboard USB 3.0 Type-A 2229 mil + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" + + # Internal Webcam 9070 mil + register "usb2_ports[CONFIG_CCD_PORT]" = "USB2_PORT_MID(OC_SKIP)" + + # Daughterboard USB 2.0 Type-A + SD Card Reader 1836 mil + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" + + # Internal Bluetooth 723 mil + register "usb2_ports[9]" = "USB2_PORT_SHORT(OC_SKIP)" + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""Left USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""Left USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""Right USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""Right USB Type-A"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""Internal Webcam"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 4)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""MicroSD Card Reader"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(0, 5)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""Internal Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "is_intel_bluetooth" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B18)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B18)" + register "group" = "ACPI_PLD_GROUP(0, 6)" + device ref usb2_port10 on end + end + end + end + end + device ref i2c0 on + chip drivers/i2c/hid + register "generic.hid" = ""STAR0001"" + register "generic.desc" = ""Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B00_IRQ)" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device ref ioe_shared_sram on end + device ref pmc_shared_sram on end + device ref pcie_rp9 on # WiFi + register "pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, + }" + smbios_slot_desc "SlotTypePciExpressGen3X1" + "SlotLengthShort" + "M.2/M 2230" + "SlotDataBusWidth1X" + + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B19)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H02)" + register "srcclk_pin" = "5" + register "add_acpi_dma_property" = "true" + register "skip_on_off_support" = "true" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "true" + device generic 0 on end + end + end + device ref pcie_rp10 on # SSD x4 + register "pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L0S_L1, + .PcieRpL1Substates = L1_SS_L1_2, + + }" + smbios_slot_desc "SlotTypeM2Socket3" + "SlotLengthLong" + "M.2/M 2280" + "SlotDataBusWidth4X" + + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H07)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H00)" + register "srcclk_pin" = "8" + register "is_storage" = "true" + register "add_acpi_dma_property" = "true" + register "skip_on_off_support" = "true" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "use_rp_mutex" = "true" + device generic 0 on end + end + end + device ref uart0 on end + device ref soc_espi on + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x00fc0201" + register "gen3_dec" = "0x000c0081" + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + + chip ec/starlabs/merlin + # Port pair 4Eh/4Fh + device pnp 4e.00 on end # IO Interface + device pnp 4e.01 off end # Com 1 + device pnp 4e.02 off end # Com 2 + device pnp 4e.04 off end # System Wake-Up + device pnp 4e.05 off end # PS/2 Mouse + device pnp 4e.06 on # PS/2 Keyboard + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 + end + device pnp 4e.0a off end # Consumer IR + device pnp 4e.0f off end # Shared Memory/Flash Interface + device pnp 4e.10 off end # RTC-like Timer + device pnp 4e.11 off end # Power Management Channel 1 + device pnp 4e.12 off end # Power Management Channel 2 + device pnp 4e.13 off end # Serial Peripheral Interface + device pnp 4e.14 off end # Platform EC Interface + device pnp 4e.17 off end # Power Management Channel 3 + device pnp 4e.18 off end # Power Management Channel 4 + device pnp 4e.19 off end # Power Management Channel 5 + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref hda on + subsystemid 0x1e50 0x7038 + register "pch_hda_sdi_enable[0]" = "true" + register "pch_hda_audio_link_hda_enable" = "true" + register "pch_hda_idisp_codec_enable" = "true" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + end + device ref smbus on end + end +end diff --git a/src/mainboard/starlabs/starbook/variants/mtl/devtree.c b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c new file mode 100644 index 0000000..a97ff8a --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/devtree.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <chip.h> +#include <cpu/intel/turbo.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <option.h> +#include <static.h> +#include <types.h> +#include <variants.h> + +void devtree_update(void) +{ + config_t *cfg = config_of_soc(); + + struct soc_intel_common_config *common_config; + common_config = chip_get_common_soc_structure(); + + struct soc_power_limits_config *soc_conf_20core = + &cfg->power_limits_config[MTL_P_682_482_CORE]; + + struct device *gna_dev = pcidev_on_root(0x08, 0); + + uint8_t performance_scale = 100; + + /* Set PL4 to 1.0C */ + soc_conf_20core->tdp_pl4 = 65; + + /* Set PL1 to 50% of PL2 */ + soc_conf_20core->tdp_pl1_override = (soc_conf_20core->tdp_pl2_override / 2) & ~1; + + /* Scale PL1 & PL2 based on CMOS settings */ + switch (get_power_profile(PP_POWER_SAVER)) { + case PP_POWER_SAVER: + performance_scale -= 50; + common_config->pch_thermal_trip = 30; + break; + case PP_BALANCED: + performance_scale -= 25; + common_config->pch_thermal_trip = 25; + break; + case PP_PERFORMANCE: + /* Use the Intel defaults */ + common_config->pch_thermal_trip = 20; + break; + } + + soc_conf_20core->tdp_pl1_override = (soc_conf_20core->tdp_pl1_override * performance_scale) / 100; + soc_conf_20core->tdp_pl2_override = (soc_conf_20core->tdp_pl2_override * performance_scale) / 100; + + /* Enable/Disable Bluetooth based on CMOS settings */ + if (get_uint_option("wireless", 1) == 0) + cfg->usb2_ports[9].enable = 0; + + /* Enable/Disable Webcam based on CMOS settings */ + if (get_uint_option("webcam", 1) == 0) + cfg->usb2_ports[CONFIG_CCD_PORT].enable = 0; + + /* Enable/Disable Card Reader based on CMOS Settings */ + if (get_uint_option("card_reader", 1) == 0) + cfg->usb2_ports[3].enable = 0; + + /* Enable/Disable GNA based on CMOS settings */ + if (get_uint_option("gna", 1) == 0) + gna_dev->enabled = 0; +} diff --git a/src/mainboard/starlabs/starbook/variants/mtl/gpio.c b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c new file mode 100644 index 0000000..4ae9d69 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/gpio.c @@ -0,0 +1,507 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variants.h> + +/* Early pad configuration in bootblock */ +const struct pad_config early_gpio_table[] = { + /* H10: UART0 RXD */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* H11: UART0 TXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + + /* C00: SMB_CLK */ + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), + /* C01: SMB_DATA */ + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Pad configuration in ramstage. */ +const struct pad_config gpio_table[] = { + /* + * GPP_V + * Start: GPP_V00 + * End: GPP_V22 + */ + /* V00: PM_BATLOW_N */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), + /* V01: CHG_ACOK */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), + /* V02: PCIE_WAKE_LAN */ + PAD_NC(GPP_V02, NONE), + /* V03: EC_PWRBTN_N */ + PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), + /* V04: PM_SLP_S3_N */ + PAD_NC(GPP_V04, NONE), + /* V05: SLP S4# */ + PAD_NC(GPP_V05, NONE), + /* V06: GPD_6_SLP_A_N */ + PAD_NC(GPP_V06, NONE), + /* V07: */ + PAD_NC(GPP_V07, NONE), + /* V08: M.2_BTWIFI_SUS_CLK */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* V09: GPD_9_SLP_WLAN_N */ + PAD_NC(GPP_V09, NONE), + /* V10: PM_SLP_S5_N */ + PAD_NC(GPP_V10, NONE), + /* V11: LANPHY_ENABLE */ + PAD_NC(GPP_V11, NONE), + /* V12: SLP_LAN_N */ + PAD_NC(GPP_V12, NONE), + /* V13 */ + PAD_NC(GPP_V13, NONE), + /* V14: WAKE_N */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* V15: */ + PAD_NC(GPP_V15, NONE), + /* V16: */ + PAD_NC(GPP_V16, NONE), + /* V17: */ + PAD_NC(GPP_V17, NONE), + /* V18: */ + PAD_NC(GPP_V18, NONE), + /* V19: */ + PAD_NC(GPP_V19, NONE), + /* V20: */ + PAD_NC(GPP_V20, NONE), + /* V21: */ + PAD_NC(GPP_V21, NONE), + /* V22: */ + PAD_NC(GPP_V22, NONE), + /* V23: */ + PAD_NC(GPP_V23, NONE), + + /* + * GPP_C + * Start: GPP_C00 + * End: GPP_C23 + */ + /* C02: TLS CONFIDENTIALITY + * HIGH: ENABLED + * LOW: DISABLED + * WEAK INTERNAL PD 20K */ + PAD_CFG_GPO(GPP_C02, 1, DEEP), + /* C03: SML0_CLK */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), + /* C04: SML0_DATA */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), + /* C05: ESPI + * HIGH: ENABLED + * LOW: DISABLED + * WEAK INTERNAL PD 20K */ + PAD_CFG_GPO(GPP_C05, 1, DEEP), + /* C06: SML1_CLK_USBC_PD_N */ + PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1), + /* C07: SML1_DATA_USBC_PD_N */ + PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1), + /* C08: SML1ALERT */ + PAD_NC(GPP_C08, NONE), + /* C09: */ + PAD_NC(GPP_C09, NONE), + /* C10: */ + PAD_NC(GPP_C10, NONE), + /* C11: */ + PAD_NC(GPP_C11, NONE), + /* C12: CLKREQ3 */ + PAD_NC(GPP_C12, NONE), + /* C13: */ + PAD_NC(GPP_C13, NONE), + /* C14: */ + PAD_NC(GPP_C14, NONE), + /* C15: RESERVED + * WEAK INTERNAL PD 20K */ + PAD_NC(GPP_C15, NONE), + /* C16: */ + PAD_NC(GPP_C16, NONE), + /* C17: */ + PAD_NC(GPP_C17, NONE), + /* C18: */ + PAD_NC(GPP_C18, NONE), + /* C19: */ + PAD_NC(GPP_C19, NONE), + /* C20: */ + PAD_NC(GPP_C20, NONE), + /* C21: */ + PAD_NC(GPP_C21, NONE), + /* C22: */ + PAD_NC(GPP_C22, NONE), + /* C23: */ + PAD_NC(GPP_C23, NONE), + + /* + * GPP_A + * Start: GPP_A00 + * End: GPP_A23 + */ + /* A00: ESPI_IO0_EC_R */ + PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), + /* A01: ESPI_IO1_EC_R */ + PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), + /* A02: ESPI_IO2_EC_R */ + PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), + /* A03: ESPI_IO3_EC_R */ + PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), + /* A04: ESPI_CS0_N */ + PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), + /* A05: ESPI_CLK_EC_R */ + PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), + /* A06: ESPI_RESET_N */ + PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), + /* A07: */ + PAD_NC(GPP_A07, NONE), + /* A08: */ + PAD_NC(GPP_A08, NONE), + /* A09: */ + PAD_NC(GPP_A09, NONE), + /* A10: */ + PAD_NC(GPP_A10, NONE), + /* A11: */ + PAD_NC(GPP_A11, NONE), + /* A12: WLAN_PEWAKE */ + PAD_CFG_GPI(GPP_A12, NONE, DEEP), + /* A13: */ + PAD_NC(GPP_A13, NONE), + /* A14: */ + PAD_NC(GPP_A14, NONE), + /* A15: */ + PAD_NC(GPP_A15, NONE), + /* A16: */ + PAD_NC(GPP_A16, NONE), + /* A17: EC_SLP_S0_CS_N */ + PAD_NC(GPP_A17, NONE), + /* A18: */ + PAD_NC(GPP_A18, NONE), + /* A19: */ + PAD_NC(GPP_A19, NONE), + /* A20: M.2_CPU_SSD_RESET_N */ + PAD_CFG_GPO(GPP_A20, 1, PLTRST), + /* A21: I2C_PMC_PD_INT_N */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + /* A22: */ + PAD_NC(GPP_A22, NONE), + /* A23: */ + PAD_NC(GPP_A23, NONE), + + /* + * GPP_E + * Start: GPP_E00 + * End: GPP_E23 + */ + /* E00: */ + PAD_NC(GPP_E00, NONE), + /* E01: */ + PAD_NC(GPP_E01, NONE), + /* E02: */ + PAD_NC(GPP_E02, NONE), + /* E03: */ + PAD_NC(GPP_E03, NONE), + /* E04: M.2_SSD_DEVSLP0 */ + /* E05: */ + PAD_NC(GPP_E05, NONE), + /* E06: JTAG ODT + * HIGH: ENABLED + * LOW: DISABLED + * 20K INTERNAL PU */ + /* E07: */ + PAD_NC(GPP_E07, NONE), + /* E08: */ + PAD_NC(GPP_E08, NONE), + /* E09: USB2_OC0 */ + /* E10: */ + PAD_NC(GPP_E10, NONE), + /* E11: */ + PAD_NC(GPP_E11, NONE), + /* E12: */ + PAD_NC(GPP_E12, NONE), + /* E13: */ + PAD_NC(GPP_E13, NONE), + /* E14: EDP_HPD_N */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15: BOOTHALT_N */ + PAD_NC(GPP_E15, NONE), + /* E16: BC_PROCHOT_N */ + PAD_CFG_GPI_SCI(GPP_E16, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* E17: */ + PAD_NC(GPP_E17, NONE), + /* E18: */ + PAD_NC(GPP_E18, NONE), + /* E19: */ + PAD_NC(GPP_E19, NONE), + /* E20: */ + PAD_NC(GPP_E20, NONE), + /* E21: */ + PAD_NC(GPP_E21, NONE), + /* E22: */ + PAD_NC(GPP_E22, NONE), + /* E23: */ + PAD_NC(GPP_E23, NONE), + + /* + * GPP_H + * Start: GPP_H00 + * End: GPP_H23 + */ + /* H00: M.2_PCH_SSD_RESET_N */ + PAD_CFG_GPO(GPP_H00, 1, PLTRST), + /* H01: FLASH RECOVERY + * HIGH: ENABLED + * LOW: DISABLED + * WEAK INTERNAL PD 20K */ + PAD_NC(GPP_H01, NONE), + /* H02: WLAN_RST_N */ + PAD_CFG_GPO(GPP_H02, 1, PLTRST), + /* H03: */ + PAD_NC(GPP_H03, NONE), + /* H04: */ + PAD_NC(GPP_H04, NONE), + /* H05: */ + PAD_NC(GPP_H05, NONE), + /* H06: */ + PAD_NC(GPP_H06, NONE), + /* H07: M.2_CPU_SSD_PWREN */ + PAD_CFG_GPO(GPP_H07, 1, PLTRST), + /* H08: */ + PAD_NC(GPP_H08, NONE), + /* H09: */ + PAD_NC(GPP_H09, NONE), + /* H10: */ + PAD_NC(GPP_H10, NONE), + /* H11: */ + PAD_NC(GPP_H11, NONE), + /* H12: */ + PAD_NC(GPP_H12, NONE), + /* H13: CPU_C10_GATE_N_R */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* H14: */ + PAD_NC(GPP_H14, NONE), + /* H15: */ + PAD_NC(GPP_H15, NONE), + /* H16: DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17: DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H18: */ + PAD_NC(GPP_H18, NONE), + /* H19: TCHPAD_I2C0_SDA_N */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* H20: TCHPAD_I2C0_SCL_N */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* H21: */ + PAD_NC(GPP_H21, NONE), + /* H22: */ + PAD_NC(GPP_H22, NONE), + /* H23: */ + PAD_NC(GPP_H23, NONE), + + /* + * GPP_F + * Start: GPP_F00 + * End: GPP_F23 + */ + /* F00: CNV_BRI_DT */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), + /* F01: CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), + /* F02: CNV_RGI_DT */ + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), + /* F03: CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), + /* F04: CNVI_RF_RESET_N */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), + /* F05: MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF3), + /* F06: */ + PAD_NC(GPP_F06, NONE), + /* F07: */ + PAD_NC(GPP_F07, NONE), + /* F08: */ + PAD_NC(GPP_F08, NONE), + /* F09: */ + PAD_NC(GPP_F09, NONE), + /* F10: SATAXPCIE_1_SATAGP_1 */ + PAD_NC(GPP_F10, NONE), + /* F11: */ + PAD_NC(GPP_F11, NONE), + /* F12: */ + PAD_NC(GPP_F12, NONE), + /* F13: TPM_IRQ */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* F14: */ + PAD_NC(GPP_F14, NONE), + /* F15: */ + PAD_NC(GPP_F15, NONE), + /* F16: */ + PAD_NC(GPP_F16, NONE), + /* F17: */ + PAD_NC(GPP_F17, NONE), + /* F18: */ + PAD_NC(GPP_F18, NONE), + /* F19: ESPI FLASH SHARING + * HIGH: MASTER + * LOW: SLAVE + * WEAK INTERNAL PD 20K */ + PAD_NC(GPP_F19, NONE), + /* F20: SVID + * HIGH: PRESENT + * LOW: NOT PRESENT + * WEAK INTERNAL PD 20K */ + PAD_NC(GPP_F20, NONE), + /* F21: CCD + * HIGH: BALTIC PEAK + * LOW: BSSB-LS + * WEAK INTERNAL PU 20K */ + /* F21: */ + PAD_NC(GPP_F21, NONE), + /* F22: */ + PAD_NC(GPP_F22, NONE), + /* F23: */ + PAD_NC(GPP_F23, NONE), + + /* + * GPP_S + * Start: GPP_S00 + * End: GPP_S07 + */ + /* S00: */ + PAD_NC(GPP_S00, NONE), + /* S01: */ + PAD_NC(GPP_S01, NONE), + /* S02: */ + PAD_NC(GPP_S02, NONE), + /* S03: */ + PAD_NC(GPP_S03, NONE), + /* S04: */ + PAD_NC(GPP_S04, NONE), + /* S05: */ + PAD_NC(GPP_S05, NONE), + /* S06: */ + PAD_NC(GPP_S06, NONE), + /* S07: */ + PAD_NC(GPP_S07, NONE), + + /* + * GPP_B + * Start: GPP_B00 + * End: GPP_B23 + */ + /* B00: TCHPAD_INT_N */ + PAD_CFG_GPI_APIC(GPP_B00, NONE, DEEP, LEVEL, INVERT), + /* B01: */ + PAD_NC(GPP_B01, NONE), + /* B02: */ + PAD_NC(GPP_B02, NONE), + /* B03: */ + PAD_NC(GPP_B03, NONE), + /* B04: REBOOT CONTROL + * HIGH: NO REBOOT + * LOW: REBOOT ENABLED + * WEAK INTERNAL PD 20K + */ + PAD_CFG_GPO(GPP_B04, 0, DEEP), + /* B05: */ + PAD_NC(GPP_B05, NONE), + /* B06: */ + PAD_NC(GPP_B06, NONE), + /* B07: */ + PAD_NC(GPP_B07, NONE), + /* B08: */ + PAD_NC(GPP_B08, NONE), + /* B09: */ + PAD_NC(GPP_B09, NONE), + /* B10: */ + PAD_NC(GPP_B10, NONE), + /* B11: */ + PAD_NC(GPP_B11, NONE), + /* B12: */ + PAD_NC(GPP_B12, NONE), + /* B13: PLT_RST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* B14: */ + PAD_NC(GPP_B14, NONE), + /* B15: */ + PAD_NC(GPP_B15, NONE), + /* B16: DDIB_DP_HPD */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17: */ + PAD_NC(GPP_B17, NONE), + /* B18: BT_RF_KILL_N */ + PAD_CFG_GPO_GPIO_DRIVER(GPP_B18, 1, DEEP, NONE), + /* B19: WIFI_RF_KILL_N */ + PAD_CFG_GPO_GPIO_DRIVER(GPP_B19, 1, DEEP, NONE), + /* B20: */ + PAD_NC(GPP_B20, NONE), + /* B21: */ + PAD_NC(GPP_B21, NONE), + /* B22: */ + PAD_NC(GPP_B22, NONE), + /* B23: */ + PAD_NC(GPP_B23, NONE), + + /* + * GPP_D + * Start: GPP_D00 + * End: GPP_D23 + */ + /* D00: */ + PAD_NC(GPP_D00, NONE), + /* D01: */ + PAD_NC(GPP_D01, NONE), + /* D02: */ + PAD_NC(GPP_D02, NONE), + /* D03: */ + PAD_NC(GPP_D03, NONE), + /* D04: */ + PAD_NC(GPP_D04, NONE), + /* D05: */ + PAD_NC(GPP_D05, NONE), + /* D06: SML0BALERT# */ + PAD_NC(GPP_D06, NONE), + /* D07: */ + PAD_NC(GPP_D07, NONE), + /* D08: */ + PAD_NC(GPP_D08, NONE), + /* D09: */ + PAD_NC(GPP_D09, NONE), + /* D10: HDA_CODEC_BCLK */ + PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF1), + /* D11: HDA_CODEC_SYNC */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), + /* D12: HDA_CODEC_SDO */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), + /* D13: HDA_CODEC_SDI */ + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), + /* D14: */ + PAD_NC(GPP_D14, NONE), + /* D15: */ + PAD_NC(GPP_D15, NONE), + /* D16: */ + PAD_NC(GPP_D16, NONE), + /* D17: HDA_CODEC_RESET0_N */ + PAD_CFG_NF(GPP_D17, NATIVE, DEEP, NF1), + /* D18: */ + PAD_NC(GPP_D18, NONE), + /* D19: */ + PAD_NC(GPP_D19, NONE), + /* D20: CLKREQ8 + * SSD */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* D21: CLKREQ5 + * WLAN */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), + /* D22: */ + PAD_NC(GPP_D22, NONE), + /* D23: */ + PAD_NC(GPP_D23, NONE), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c b/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c new file mode 100644 index 0000000..89de21c --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/hda_verb.c @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> +#include <stdint.h> + +#define DMIC 0x12 +#define SPEAKERS 0x14 +#define HEADPHONE 0x15 +#define MONO 0x17 +#define MIC1 0x18 +#define MIC2 0x19 +#define LINE1 0x1a +#define LINE2 0x1b +#define PC_BEEP 0x1d +#define S_PDIF 0x1e + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, /* Codec Vendor / Device ID: Realtek ALC269 */ + 0x1e507038, /* Subsystem ID */ + 18, /* Number of verb entries */ + + /* Reset Codec First */ + AZALIA_RESET(0x1), + + /* HDA Codec Subsystem ID */ + AZALIA_SUBVENDOR(0, 0x1e507038), + + AZALIA_PIN_CFG(0, 0x01, 0x00000000), + AZALIA_PIN_CFG(0, DMIC, AZALIA_PIN_DESC( \ + AZALIA_INTEGRATED, \ + AZALIA_INTERNAL | AZALIA_TOP, \ + AZALIA_MIC_IN, \ + AZALIA_TYPE_UNKNOWN, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 3, \ + 0 \ + )), + + AZALIA_PIN_CFG(0, SPEAKERS, AZALIA_PIN_DESC( \ + AZALIA_INTEGRATED, \ + AZALIA_INTERNAL | AZALIA_FRONT, \ + AZALIA_SPEAKER, \ + AZALIA_TYPE_UNKNOWN, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 1, \ + 0 \ + )), + AZALIA_PIN_CFG(0, HEADPHONE, AZALIA_PIN_DESC( \ + AZALIA_JACK, \ + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, \ + AZALIA_HP_OUT, \ + AZALIA_STEREO_MONO_1_8, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 2, \ + 0 \ + )), + AZALIA_PIN_CFG(0, MONO, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, MIC1, AZALIA_PIN_DESC( \ + AZALIA_JACK, \ + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, \ + AZALIA_MIC_IN, \ + AZALIA_STEREO_MONO_1_8, \ + AZALIA_BLACK, \ + AZALIA_JACK_PRESENCE_DETECT, \ + 4, \ + 0 \ + )), + AZALIA_PIN_CFG(0, MIC2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, LINE1, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, LINE2, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, PC_BEEP, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, S_PDIF, AZALIA_PIN_CFG_NC(0)), + + 0x02050018, + 0x02040184, + + 0x0205001C, + 0x02044b00, + + 0x02050024, + 0x02040000, + + 0x02050004, + 0x02040080, + + 0x02050008, + 0x02040000, + + 0x0205000C, + 0x02043F00, + + 0x02050015, + 0x02048002, + + 0x02050015, + 0x02048002, + + 0x00C37080, + 0x00270610, + 0x00D37080, + 0x00370610, + + 0x8086280d, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of 4 dword sets */ + + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c new file mode 100644 index 0000000..c01c4dd1 --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/ramstage.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <soc/ramstage.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *supd) +{ + /* + * FSP defaults to pins that are used for LPC; given that + * coreboot only supports eSPI, set these pins accordingly. + */ + supd->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + supd->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 +} diff --git a/src/mainboard/starlabs/starbook/variants/mtl/romstage.c b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c new file mode 100644 index 0000000..beb623c --- /dev/null +++ b/src/mainboard/starlabs/starbook/variants/mtl/romstage.c @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <option.h> +#include <soc/meminit.h> +#include <soc/romstage.h> +#include <types.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg mem_config = { + .type = MEM_TYPE_DDR5, + }; + + const bool half_populated = false; + + const struct mem_spd ddr4_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { + .addr_dimm[0] = 0x52, + }, + }, + }; + + memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated); + + const uint8_t vtd = get_uint_option("vtd", 1); + mupd->FspmConfig.VtdDisable = !vtd; + + /* Enable/Disable Wireless (RP09) based on CMOS settings */ + if (get_uint_option("wireless", 1) == 0) + mupd->FspmConfig.PcieRpEnableMask &= ~(1 << 8); + + mupd->FspmConfig.PchHdaSubSystemIds = 0x14f1035e; +};
-
Sean Rhodes (Code Review)