[XS] Change in coreboot[main]: Brox: ISH: Reconfigure pins to reduce power

[Yuval Peress (Code Review)]

Yuval Peress has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82260?usp=email )

Change subject: Brox: ISH: Reconfigure pins to reduce power
......................................................................

Brox: ISH: Reconfigure pins to reduce power

D2 needs a pull-up resistor
D3 is not connected and needs a pull-up resistor
D13 is not connected and needs a pull-down resistor
D14 is not connected and keeps the same pull-down resistor

Change-Id: I7ed090ba9c778373e22c849c928b76443e0a52db
---
M src/mainboard/google/brox/variants/brox/fw_config.c
1 file changed, 4 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/82260/1

diff --git a/src/mainboard/google/brox/variants/brox/fw_config.c b/src/mainboard/google/brox/variants/brox/fw_config.c
index 3962991..8ba9e68 100644
--- a/src/mainboard/google/brox/variants/brox/fw_config.c
+++ b/src/mainboard/google/brox/variants/brox/fw_config.c
@@ -18,13 +18,13 @@
    /* GPP_B15 : ISH_GP7, LID_OPEN_1V8 */
    PAD_CFG_NF(GPP_B15, NONE, DEEP, NF5),
    /* GPP_D2 : ISH_GP2, SOC_ISH_ACCEL_INT_L */
-	PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_D2, UP_20K, DEEP, NF1),
    /* GPP_D3 : ISH_GP3, SOC_ISH_IMU_INT_L */
-	PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1),
+	PAD_NC(GPP_D3, UP_20K),
    /* GPP_D13 : [NF1: ISH_UART0_RXD ==> UART0_ISH_RX_DBG_TX */
-	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	PAD_NC(GPP_D13, DN_20K),
    /* GPP_D14 : [NF1: ISH_UART0_TXD ==> UART0_ISH_TX_DBG_RX */
-	PAD_CFG_NF(GPP_D14, DN_20K, DEEP, NF1),
+	PAD_NC(GPP_D14, DN_20K),
    /* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> NOTE_BOOK_MODE */
    PAD_CFG_NF(GPP_E9, NONE, PLTRST, NF2),
 };