Change in coreboot[master]: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB - coreboot-gerrit

4 Jun 2021


      Attention is currently required from: Jason Glenesk, Marshall Dawson, Nikolai Vyssotski, Matt Papageorge, Felix Held.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55237 )
Change subject: soc/amd/common/fsp/pci: Add size field to PCIe interrupt routing HOB
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Patch Set 5: Code-Review+2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20
Gerrit-Change-Number: 55237
Gerrit-PatchSet: 5
Gerrit-Owner: Nikolai Vyssotski nikolai.vyssotski@amd.corp-partner.google.com
Gerrit-Reviewer: Felix Held felix-coreboot@felixheld.de
Gerrit-Reviewer: Jason Glenesk jason.glenesk@gmail.com
Gerrit-Reviewer: Marshall Dawson marshalldawson3rd@gmail.com
Gerrit-Reviewer: Matt Papageorge matthewpapa07@gmail.com
Gerrit-Reviewer: Raul Rangel rrangel@chromium.org
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Gerrit-Comment-Date: Fri, 04 Jun 2021 22:42:27 +0000
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