[M] Change in coreboot[main]: skl mainboards/dt: Move SATA related settings into SATA device scope
Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/83179?usp=email )
Change subject: skl mainboards/dt: Move SATA related settings into SATA device scope ......................................................................
skl mainboards/dt: Move SATA related settings into SATA device scope
Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/83179 Reviewed-by: Eric Lai ericllai@google.com Reviewed-by: Erik van den Bogaert ebogaert@eltan.com Reviewed-by: Marvin Evers marvin.n.evers@gmail.com Reviewed-by: Jonathon Hall jonathon.hall@puri.sm Reviewed-by: Michael Niewöhner foss@mniewoehner.de Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 12 files changed, 108 insertions(+), 94 deletions(-)
Approvals: Eric Lai: Looks good to me, approved Michael Niewöhner: Looks good to me, but someone else must approve Jonathon Hall: Looks good to me, but someone else must approve build bot (Jenkins): Verified Marvin Evers: Looks good to me, but someone else must approve Erik van den Bogaert: Looks good to me, but someone else must approve
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 7a77e64..1f2fa40 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -30,15 +30,6 @@ register "dptf_enable" = "0"
# FSP Configuration - register "SataSalpSupport" = "1" - - # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsDevSlp[2]" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" @@ -106,7 +97,21 @@ end device ref thermal on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + + # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + end device ref pcie_rp3 on end device ref pcie_rp4 on end device ref pcie_rp9 on end diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 854b887..c41a26f 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -32,11 +32,6 @@ register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled"
- register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - }" - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s register "PmConfigSlpS3MinAssert" = "2" @@ -209,7 +204,10 @@ device ref south_xdci on end device ref thermal on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + end device ref pcie_rp3 on end # x1 baseboard WWAN device ref pcie_rp6 on end # x1 baseboard i210 device ref pcie_rp9 on end # x4 FPGA diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 7d11653..9458c81 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -59,9 +59,6 @@ register "s0ix_enable" = true
# FSP Configuration - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[1]" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SkipExtGfxScan" = "1" @@ -359,7 +356,13 @@ device ref i2c0 on end device ref i2c2 on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + }" + register "SataPortsDevSlp[1]" = "1" + end device ref uart2 on end device ref i2c5 on end device ref pcie_rp1 on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index f2e569d..49edccb 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -47,17 +47,6 @@ register "SsicPortEnable" = "1"
- register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -112,7 +101,19 @@ device ref sa_thermal off end device ref i2c2 off end device ref i2c3 off end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref i2c4 off end device ref emmc off end device ref sdxc off end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 87bf0d8..99963bf 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -1,11 +1,5 @@ chip soc/intel/skylake
- register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - }" - # Enable deep Sx states register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" @@ -155,7 +149,13 @@ end device ref i2c2 off end device ref i2c3 off end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + end device ref pcie_rp3 on end device ref pcie_rp4 on end device ref pcie_rp5 on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 8e70c1e..5516fee 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -98,18 +98,6 @@
register "SsicPortEnable" = "1" # Enable SSIC for WWAN
- register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }" - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -164,7 +152,19 @@ end device ref i2c2 off end device ref i2c3 off end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref i2c4 off end device ref pcie_rp1 off end device ref pcie_rp3 on end diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 067cb59..73df651 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -130,17 +130,6 @@
# Must leave UART0 enabled or SD/eMMC will not work as PCI
- register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -205,7 +194,19 @@ device ref i2c2 on end device ref i2c3 on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref uart2 on end device ref i2c5 on end device ref i2c4 on end diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb index 6657fa9..b6b3574 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -8,8 +8,6 @@ register "PcieRpEnable[ 3]" = "1" register "PcieRpEnable[11]" = "1"
- register "SataPortsEnable[3]" = "1" - device domain 0 on device ref south_xhci on register "usb2_ports" = "{ @@ -26,6 +24,9 @@ [3] = USB3_PORT_DEFAULT(OC1), }" end + device ref sata on + register "SataPortsEnable[3]" = "1" + end device ref pcie_rp1 on end device ref pcie_rp2 on end device ref pcie_rp3 on end diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index f173e1e..02c3538 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -29,12 +29,6 @@ register "dptf_enable" = "0"
# FSP Configuration - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - }" - register "SataSpeedLimit" = "2" register "DspEnable" = "1" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" @@ -154,7 +148,14 @@ device ref south_xdci on end device ref thermal on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + register "SataSpeedLimit" = "2" + end device ref pcie_rp3 on end device ref pcie_rp5 on smbios_slot_desc "SlotTypePciExpressMini52pinWithoutBSKO" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 0b5d0cd..5565064 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -101,10 +101,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2"
- # Enable SATA ports 1,2 - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - # Enable Root ports. 1-6 for LAN and Root Port 9 register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" @@ -183,7 +179,12 @@ }" end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + }" + end device ref pcie_rp1 on end device ref pcie_rp2 on end device ref pcie_rp3 on end diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 5b222fc..7892c7e 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -38,8 +38,6 @@ register "dptf_enable" = "0"
# FSP Configuration - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[2]" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" @@ -146,7 +144,12 @@ device ref south_xhci on end device ref south_xdci on end device ref thermal on end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [2] = 1, + }" + end device ref pcie_rp5 on end device ref pcie_rp9 on end device ref lpc_espi on diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 1a8be1d..29759fd 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -3,18 +3,6 @@ # FSP Configuration register "SkipExtGfxScan" = "1"
- # SATA configuration - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }"
# LPC register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -31,7 +19,19 @@ device ref south_xhci on end device ref thermal on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref lpc_espi on chip superio/common device pnp 2e.0 on end
-
Felix Singer (Code Review)