[S] Change in coreboot[main]: mb/google/fatcat/var/felino: Enable Type-C Ports and TBT

[Weimin Wu (Code Review)]

Weimin Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/86633?usp=email )

Change subject: mb/google/fatcat/var/felino: Enable Type-C Ports and TBT
......................................................................

mb/google/fatcat/var/felino: Enable Type-C Ports and TBT

Test with PDC fw 19.16.3.

BUG=b:397313651
TEST=
1. FW_NAME=felino emerge-fatcat coreboot-private-files-baseboard-fatcat coreboot chromeos-bootimage
2. Type-C Ports and TBT work fine.

Change-Id: Icbed4d16911665e820382a483607e6dae44b7f8c
Signed-off-by: Weimin Wu 
---
M src/mainboard/google/fatcat/variants/felino/gpio.c
M src/mainboard/google/fatcat/variants/felino/overridetree.cb
2 files changed, 27 insertions(+), 16 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/86633/1

diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index e5ca754..a32d44b7 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -68,7 +68,7 @@
    /* GPP_B09:     NC */
    PAD_NC(GPP_B09, NONE),
    /* GPP_B10:     SOC_DP1_HDMI_HPD */
-	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_B10, NONE, DEEP, NF2),
    /* GPP_B11:     PD1_OC_P0_P1_N */
    PAD_NC(GPP_B11, NONE),
    /* GPP_B12:     SLP_S0_SOC_N */
@@ -137,9 +137,9 @@
    /* GPP_C17:     NC  */
    PAD_NC(GPP_C17, NONE),
    /* GPP_C18:     TCP3_DDC_SCL  */
-	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C18, NONE, DEEP, NF2),
    /* GPP_C19:     TCP3_DDC_SDA */
-	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+	PAD_CFG_NF(GPP_C19, NONE, DEEP, NF2),
    /* GPP_C20:     TBT_LSX1_TXD */
    PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
    /* GPP_C21:     TBT_LSX1_RXD */
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 6b4d32e..c13aa43 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -34,11 +34,17 @@
    register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0
    register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1
    register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0  # USB HUB (USB2 Camera)
-	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A Port A1 /
+	register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # Type-A Port A1 /
    register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT

register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #2 /

+	register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+	register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
+
+	register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+	register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN"
+
    #gpe configuration
    register "pmc_gpe0_dw0" = "GPP_A"
    register "pmc_gpe0_dw1" = "GPP_D"
@@ -83,6 +89,9 @@

device ref iaa off end

+device ref tbt_pcie_rp0 on end
+		device ref tbt_pcie_rp2 on end
+		device ref tbt_pcie_rp3 on end
    	device ref tcss_xhci on
    		chip drivers/usb/acpi
    			device ref tcss_root_hub on
@@ -93,7 +102,7 @@
    					device ref tcss_usb3_port2 on end
    				end
    				chip drivers/usb/acpi
-						register "desc" = ""USB3 Type-C Port C3""
+						register "desc" = ""USB3 Type-C Port C1""
    					register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
    					register "group" = "ACPI_PLD_GROUP(1, 2)"
    					device ref tcss_usb3_port3 on end
@@ -102,6 +111,19 @@
    		end
    	end

+		device ref tcss_dma1 on
+			chip drivers/intel/usb4/retimer
+				register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F11)"
+				use tcss_usb3_port3 as dfp[0].typec_port
+				device generic 0 on end
+			end
+			chip drivers/intel/usb4/retimer
+				register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F11)"
+				use tcss_usb3_port2 as dfp[1].typec_port
+				device generic 0 on end
+			end
+		end
+
    	device ref xhci on
    		chip drivers/usb/acpi
    			device ref xhci_root_hub on
@@ -145,17 +167,6 @@
    		end
    	end

-		device ref tcss_dma1 on
-			chip drivers/intel/usb4/retimer
-				use tcss_usb3_port2 as dfp[0].typec_port
-				device generic 0 on end
-			end
-			chip drivers/intel/usb4/retimer
-				use tcss_usb3_port3 as dfp[1].typec_port
-				device generic 0 on end
-			end
-		end
-
    	device ref pcie_rp1 on
    		# Enable PCH PCIE x1 slot using CLK 2
    		register "pcie_rp[PCIE_RP(3)]" = "{