Change in coreboot[master]: [WIP,RFC] sb,soc/intel: Remove option power on after fail from SMI

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Patrick Rudolph.
Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/55238 )

Change subject: [WIP,RFC] sb,soc/intel: Remove option power_on_after_fail from SMI
......................................................................

[WIP,RFC] sb,soc/intel: Remove option power_on_after_fail from SMI

The mechanism was flawed. In the case that nvram contents were
modified runtime, it still required entry to ACPI S5 for the
related control registers in PCI config space to be written.

Should it happen that there was a power failure before a first
proper shutdown, new option setting would not be honoured.

Change-Id: I4ae6aa08177d4915a7acd5a53e0aae1e968e60a2
Signed-off-by: Kyösti Mälkki 
---
M src/soc/intel/broadwell/pch/smihandler.c
M src/southbridge/intel/common/smihandler.c
M src/southbridge/intel/lynxpoint/smihandler.c
3 files changed, 6 insertions(+), 63 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/55238/1

diff --git a/src/soc/intel/broadwell/pch/smihandler.c b/src/soc/intel/broadwell/pch/smihandler.c
index a8e2067..43d4fba 100644
--- a/src/soc/intel/broadwell/pch/smihandler.c
+++ b/src/soc/intel/broadwell/pch/smihandler.c
@@ -13,7 +13,6 @@
 #include <spi-generic.h>
 #include <elog.h>
 #include <halt.h>
-#include <option.h>
 #include <soc/lpc.h>
 #include <soc/nvs.h>
 #include <soc/pci_devs.h>
@@ -125,21 +124,6 @@
    printk(BIOS_INFO, "Backlight turned off\n");
 }

-static int power_on_after_fail(void)
-{
-	/* save and recover RTC port values */
-	u8 tmp70, tmp72;
-	tmp70 = inb(0x70);
-	tmp72 = inb(0x72);
-	const unsigned int s5pwr = get_uint_option("power_on_after_fail",
-					 CONFIG_MAINBOARD_POWER_FAILURE_STATE);
-	outb(tmp70, 0x70);
-	outb(tmp72, 0x72);
-
-	/* For "KEEP", switch to "OFF" - KEEP is software emulated. */
-	return (s5pwr == MAINBOARD_POWER_ON);
-}
-
 static void southbridge_smi_sleep(void)
 {
    u32 reg32;
@@ -195,11 +179,8 @@
    	/* Disable all GPE */
    	disable_all_gpe();

-		/* Always set the flag in case CMOS was changed on runtime. */
-		if (power_on_after_fail())
-			pci_and_config8(PCH_DEV_LPC, GEN_PMCON_3, ~1);
-		else
-			pci_or_config8(PCH_DEV_LPC, GEN_PMCON_3, 1);
+		/* Set which state system will be after power reapplied */
+		lpc_set_power_failure_state(false);

/* also iterates over all bridges on bus 0 */
    	busmaster_disable_on_bus(0);
diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c
index 798f2f1..e2a99d2 100644
--- a/src/southbridge/intel/common/smihandler.c
+++ b/src/southbridge/intel/common/smihandler.c
@@ -11,7 +11,6 @@
 #include <cpu/intel/em64t101_save_state.h>
 #include <elog.h>
 #include <halt.h>
-#include <option.h>
 #include <southbridge/intel/common/pmbase.h>
 #include <smmstore.h>

@@ -93,21 +92,6 @@
 {
 }

-static int power_on_after_fail(void)
-{
-	/* save and recover RTC port values */
-	u8 tmp70, tmp72;
-	tmp70 = inb(0x70);
-	tmp72 = inb(0x72);
-	const unsigned int s5pwr = get_uint_option("power_on_after_fail",
-					 CONFIG_MAINBOARD_POWER_FAILURE_STATE);
-	outb(tmp70, 0x70);
-	outb(tmp72, 0x72);
-
-	/* For "KEEP", switch to "OFF" - KEEP is software emulated. */
-	return (s5pwr == MAINBOARD_POWER_ON);
-}
-
 static void southbridge_smi_sleep(void)
 {
    u32 reg32;
@@ -158,11 +142,8 @@

write_pmbase32(GPE0_EN, 0);

-		/* Always set the flag in case CMOS was changed on runtime. */
-		if (power_on_after_fail())
-			pci_and_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, ~1);
-		else
-			pci_or_config8(PCI_DEV(0, 0x1f, 0), D31F0_GEN_PMCON_3, 1);
+		/* Set which state system will be after power reapplied */
+		lpc_set_power_failure_state(false);

/* also iterates over all bridges on bus 0 */
    	busmaster_disable_on_bus(0);
diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c
index 769cacb..9fe93b0 100644
--- a/src/southbridge/intel/lynxpoint/smihandler.c
+++ b/src/southbridge/intel/lynxpoint/smihandler.c
@@ -10,7 +10,6 @@
 #include <cpu/intel/em64t101_save_state.h>
 #include <elog.h>
 #include <halt.h>
-#include <option.h>
 #include <southbridge/intel/common/finalize.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <cpu/intel/haswell/haswell.h>
@@ -76,21 +75,6 @@
    }
 }

-static int power_on_after_fail(void)
-{
-	/* save and recover RTC port values */
-	u8 tmp70, tmp72;
-	tmp70 = inb(0x70);
-	tmp72 = inb(0x72);
-	const unsigned int s5pwr = get_uint_option("power_on_after_fail",
-					 CONFIG_MAINBOARD_POWER_FAILURE_STATE);
-	outb(tmp70, 0x70);
-	outb(tmp72, 0x72);
-
-	/* For "KEEP", switch to "OFF" - KEEP is software emulated. */
-	return (s5pwr == MAINBOARD_POWER_ON);
-}
-
 static void southbridge_smi_sleep(void)
 {
    u32 reg32;
@@ -144,11 +128,8 @@
    	/* Disable all GPE */
    	disable_all_gpe();

-		/* Always set the flag in case CMOS was changed on runtime. */
-		if (power_on_after_fail())
-			pci_and_config8(PCH_LPC_DEV, GEN_PMCON_3, ~1);
-		else
-			pci_or_config8(PCH_LPC_DEV, GEN_PMCON_3, 1);
+		/* Set which state system will be after power reapplied */
+		lpc_set_power_failure_state(false);

/* also iterates over all bridges on bus 0 */
    	busmaster_disable_on_bus(0);