Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38527 )
Change subject: mb/intel/tglrvp: Enable RP11 for Optane ......................................................................
mb/intel/tglrvp: Enable RP11 for Optane
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device and NVMe Optane memory. Storage device uses rp9 and optane memory uses rp11. This patch enables rp11. Please note that these two share clk pins.
This is also dependent on pciecontroller3 config to be set as 2x2 instead of 1x4 in fit configuration in IFWI.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from Optane and check 2 NVMe devices from lspci
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ic81244bebac78102af7ba6308ab64b18c886f839 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/38527/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index fbd1c39..bb60a74 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -35,7 +35,7 @@ register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1"
register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[2]" = "2" @@ -135,8 +135,8 @@ device pci 1c.6 off end # RP7 0xA0BE device pci 1c.7 off end # RP8 0xA0BF device pci 1d.0 on end # RP9 0xA0B0 - device pci 1d.1 on end # RP10 0xA0B1 - device pci 1d.2 off end # RP11 0xA0B2 + device pci 1d.1 off end # RP10 0xA0B1 + device pci 1d.2 on end # RP11 0xA0B2 device pci 1d.3 off end # RP12 0xA0B3 device pci 1e.0 off end # UART0 0xA0A8 device pci 1e.1 off end # UART1 0xA0A9
Wonkyu Kim has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/38527 )
Change subject: mb/intel/tglrvp: Enable rp11 for optane ......................................................................
mb/intel/tglrvp: Enable rp11 for optane
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device and NVMe Optane memory. Storage device uses rp9 and optane memory uses rp11. This patch enables rp11. Please note that these two share clk pins.
This is also dependent on pciecontroller3 config to be set as 2x2 instead of 1x4 in fit configuration in IFWI.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from Optane and check 2 NVMe devices from lspci
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ic81244bebac78102af7ba6308ab64b18c886f839 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/38527/2
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38527 )
Change subject: mb/intel/tglrvp: Enable rp11 for optane ......................................................................
Patch Set 2: Code-Review+1
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38527 )
Change subject: mb/intel/tglrvp: Enable rp11 for optane ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/38527/2/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38527/2/src/mainboard/intel/tglrvp/... PS2, Line 38: 10 The last patchset set rp9. What was at rp9? Did the root port for optane move from 9 to 10?
Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38527 )
Change subject: mb/intel/tglrvp: Enable rp11 for optane ......................................................................
Patch Set 2: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/38527/2/src/mainboard/intel/tglrvp/... File src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/38527/2/src/mainboard/intel/tglrvp/... PS2, Line 38: 10
The last patchset set rp9. […]
we found bug recently. it's bug for using rp10 for optane. rp9 and rp11 are correct for optane.
Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38527 )
Change subject: mb/intel/tglrvp: Enable rp11 for optane ......................................................................
Patch Set 2: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38527 )
Change subject: mb/intel/tglrvp: Enable rp11 for optane ......................................................................
mb/intel/tglrvp: Enable rp11 for optane
Optane memory module shows up as 2 NVMe devices in x2 config - NVMe storage device and NVMe Optane memory. Storage device uses rp9 and optane memory uses rp11. This patch enables rp11. Please note that these two share clk pins.
This is also dependent on pciecontroller3 config to be set as 2x2 instead of 1x4 in fit configuration in IFWI.
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from Optane and check 2 NVMe devices from lspci
Signed-off-by: Wonkyu Kim wonkyu.kim@intel.com Change-Id: Ic81244bebac78102af7ba6308ab64b18c886f839 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38527 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Wonkyu Kim wonkyu.kim@intel.corp-partner.google.com Reviewed-by: Nick Vaccaro nvaccaro@google.com --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved Wonkyu Kim: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 01e0f3f..e7bfe33 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -35,7 +35,7 @@ register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" - register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1"
register "PcieClkSrcClkReq[1]" = "1" register "PcieClkSrcClkReq[2]" = "2" @@ -139,8 +139,8 @@ device pci 1c.6 off end # RP7 0xA0BE device pci 1c.7 off end # RP8 0xA0BF device pci 1d.0 on end # RP9 0xA0B0 - device pci 1d.1 on end # RP10 0xA0B1 - device pci 1d.2 off end # RP11 0xA0B2 + device pci 1d.1 off end # RP10 0xA0B1 + device pci 1d.2 on end # RP11 0xA0B2 device pci 1d.3 off end # RP12 0xA0B3 device pci 1e.0 off end # UART0 0xA0A8 device pci 1e.1 off end # UART1 0xA0A9
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38527 )
Change subject: mb/intel/tglrvp: Enable rp11 for optane ......................................................................
Patch Set 3:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/272 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/271 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/270
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Nick Vaccaro (Code Review)
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Patrick Georgi (Code Review)
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Wonkyu Kim (Code Review)