Hello Bob Moragues,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/37645
to review the following change.
Change subject: mushu: Create initial build ......................................................................
mushu: Create initial build
Create initial overlays and build for mushu
BUG=b:144857888 TEST=./build_packages --board mushu && ./build_image --board mushu --noenable_rootfs_verification test CQ-DEPEND=CL:*2190595, CL:1925296, CL:1927064, CL:1931420, CL:1934468
Signed-off-by: Bob Moragues moragues@google.com Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e --- M Documentation/releases/coreboot-4.11-relnotes.md M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/mushu/Makefile.inc A src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/mushu/include/variant/ec.h A src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h A src/mainboard/google/hatch/variants/mushu/overridetree.cb 9 files changed, 224 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37645/1
diff --git a/Documentation/releases/coreboot-4.11-relnotes.md b/Documentation/releases/coreboot-4.11-relnotes.md index 890c2d7..ee5c4bf 100644 --- a/Documentation/releases/coreboot-4.11-relnotes.md +++ b/Documentation/releases/coreboot-4.11-relnotes.md @@ -75,6 +75,7 @@ * GOOGLE JUNIPER * GOOGLE KAKADU * GOOGLE KAPPA +* GOOGLE MUSHU * GOOGLE PUFF * GOOGLE SARIEN CML * GOOGLE TREEYA diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 98a0174..51d736b 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -95,6 +95,7 @@ default "Jinlon" if BOARD_GOOGLE_JINLON default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU + default "Mushu" if BOARD_GOOGLE_MUSHU default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE
@@ -121,6 +122,7 @@ default "jinlon" if BOARD_GOOGLE_JINLON default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU + default "mushu" if BOARD_GOOGLE_MUSHU default "puff" if BOARD_GOOGLE_PUFF default "stryke" if BOARD_GOOGLE_STRYKE
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index ed90de6..9532d75 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -38,6 +38,12 @@ select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011
+config BOARD_GOOGLE_MUSHU + bool "-> Mushu" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_32768 + select ROMSTAGE_SPD_SMBUS + config BOARD_GOOGLE_PUFF bool "-> Puff" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc new file mode 100644 index 0000000..30daaf7 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc @@ -0,0 +1,16 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c new file mode 100644 index 0000000..b8b54d3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* B14 : GPP_B14_STRAP */ + PAD_NC(GPP_B14, NONE), + /* B22 : GPP_B22_STRAP */ + PAD_NC(GPP_B22, NONE), + /* E19 : GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E21 : GPP_E21_STRAP */ + PAD_NC(GPP_E21, NONE), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..2c44a82 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl @@ -0,0 +1 @@ +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h b/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h new file mode 100644 index 0000000..768987d --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h new file mode 100644 index 0000000..d99e2bb --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb new file mode 100644 index 0000000..d5e2e5a --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -0,0 +1,100 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | RFU | + #| I2C2 | PS175 | + #| I2C3 | MST | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 0, + .fall_time_ns = 0, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 15.0 off + # RFU - Reserved for Future Use. + end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 on +# chip drivers/i2c/generic +# register "name" = ""PS175"" +# register "desc" = ""PCON PS175"" +# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" +# register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C11)" +# register "has_power_resource" = "1" +# device i2c 15 on end +# end + end # I2C #2 + device pci 15.3 on +# chip drivers/i2c/generic +# register "name" = ""RTD21"" +# register "desc" = ""Realtek RTD2142"" +# device i2c 4a on end +# end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 off end # GSPI #1 + end + +end
Hello YH Lin, Rajat Jain, Tim Wawrzynczak, Philip Chen, Bob Moragues, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37645
to look at the new patch set (#2).
Change subject: mushu: Create initial build ......................................................................
mushu: Create initial build
Create initial overlays and build for mushu
Signed-off-by: Bob Moragues moragues@chromium.org> Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e --- M Documentation/releases/coreboot-4.11-relnotes.md M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/mushu/Makefile.inc A src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/mushu/include/variant/ec.h A src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h A src/mainboard/google/hatch/variants/mushu/overridetree.cb 9 files changed, 224 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37645/2
Hello YH Lin, Rajat Jain, Tim Wawrzynczak, Philip Chen, Bob Moragues, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37645
to look at the new patch set (#3).
Change subject: mushu: Create initial build ......................................................................
mushu: Create initial build
Create initial overlays and build for mushu
Signed-off-by: Bob Moragues moragues@chromium.org> Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e --- M Documentation/releases/coreboot-4.11-relnotes.md M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/mushu/Makefile.inc A src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/mushu/include/variant/ec.h A src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h A src/mainboard/google/hatch/variants/mushu/overridetree.cb 9 files changed, 224 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37645/3
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mushu: Create initial build ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37645/3/Documentation/releases/core... File Documentation/releases/coreboot-4.11-relnotes.md:
https://review.coreboot.org/c/coreboot/+/37645/3/Documentation/releases/core... PS3, Line 78: * GOOGLE MUSHU IIUC, 4.11 was already "released" so this board didn't make it in.
Hello YH Lin, Rajat Jain, Tim Wawrzynczak, Philip Chen, Bob Moragues, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37645
to look at the new patch set (#4).
Change subject: mushu: Create initial build ......................................................................
mushu: Create initial build
Create initial overlays and build for mushu
Signed-off-by: Bob Moragues moragues@chromium.org> Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/mushu/Makefile.inc A src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/mushu/include/variant/ec.h A src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h A src/mainboard/google/hatch/variants/mushu/overridetree.cb 8 files changed, 223 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37645/4
Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mushu: Create initial build ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37645/3/Documentation/releases/core... File Documentation/releases/coreboot-4.11-relnotes.md:
https://review.coreboot.org/c/coreboot/+/37645/3/Documentation/releases/core... PS3, Line 78: * GOOGLE MUSHU
IIUC, 4.11 was already "released" so this board didn't make it in.
Done
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mushu: Create initial build ......................................................................
Patch Set 4:
(8 comments)
https://review.coreboot.org/c/coreboot/+/37645/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37645/4//COMMIT_MSG@7 PS4, Line 7: mushu: Create initial build mb/google/hatch: Add mushu variant
https://review.coreboot.org/c/coreboot/+/37645/4//COMMIT_MSG@11 PS4, Line 11: >> One `>` too much?
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 11: [PchSerialIoIndexSPI1] = PchSerialIoPci, This is off later in the devtree.
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 26: RFU The meaning of "RFU" isn't obvious. I'd rather use the full "Reserved for future use" phrase.
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 27: PS175 What is this? I would rather specify the function of this device (touchscreen, touchpad, scaler...) here.
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 28: MST Is this MStar? If so, why does the devtree say Realtek RTD2142 later?
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 36: i2c[0] This is disabled, so I guess this could be dropped
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 41: .i2c[1] Did you mean `.i2c[2]` ?
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mushu: Create initial build ......................................................................
Patch Set 4:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 28: MST
Is this MStar? If so, why does the devtree say Realtek RTD2142 later?
Multi Stream Transport
Hello YH Lin, Rajat Jain, Angel Pons, Tim Wawrzynczak, Philip Chen, Bob Moragues, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37645
to look at the new patch set (#5).
Change subject: mb/google/hatch: Add mushu variant ......................................................................
mb/google/hatch: Add mushu variant
Create initial overlays and build for mushu
Signed-off-by: Bob Moragues moragues@chromium.org Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/mushu/Makefile.inc A src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/mushu/include/variant/ec.h A src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h A src/mainboard/google/hatch/variants/mushu/overridetree.cb 8 files changed, 223 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37645/5
Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mb/google/hatch: Add mushu variant ......................................................................
Patch Set 5:
(2 comments)
Looking at review comments for overridetree.cb. This is a currently a direct copy of the hatch/puff version. The hatch/mushu version may or may not change going forward.
https://review.coreboot.org/c/coreboot/+/37645/4//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/37645/4//COMMIT_MSG@7 PS4, Line 7: mushu: Create initial build
mb/google/hatch: Add mushu variant
Done
https://review.coreboot.org/c/coreboot/+/37645/4//COMMIT_MSG@11 PS4, Line 11: >>
One `>` too much?
Done
Hello YH Lin, Rajat Jain, Angel Pons, Tim Wawrzynczak, Philip Chen, Bob Moragues, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37645
to look at the new patch set (#6).
Change subject: mb/google/hatch: Add mushu variant ......................................................................
mb/google/hatch: Add mushu variant
Create initial overlays and build for mushu
Signed-off-by: Bob Moragues moragues@chromium.org Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/mushu/Makefile.inc A src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/mushu/include/variant/ec.h A src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h A src/mainboard/google/hatch/variants/mushu/overridetree.cb 8 files changed, 345 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37645/6
Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mb/google/hatch: Add mushu variant ......................................................................
Patch Set 6:
(6 comments)
Mushu variant is initially mirroring Hatch reference. It is expected to change over time.
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 11: [PchSerialIoIndexSPI1] = PchSerialIoPci,
This is off later in the devtree.
Switched to mirror Hatch reference laptop.
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 26: RFU
The meaning of "RFU" isn't obvious. I'd rather use the full "Reserved for future use" phrase.
Switched to mirror Hatch reference laptop.
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 27: PS175
What is this? I would rather specify the function of this device (touchscreen, touchpad, scaler... […]
Switched to mirror Hatch reference laptop.
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 28: MST
Multi Stream Transport
Switched to mirror Hatch reference laptop.
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 36: i2c[0]
This is disabled, so I guess this could be dropped
Switched to mirror Hatch reference laptop.
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 41: .i2c[1]
Did you mean `. […]
Switched to mirror Hatch reference laptop.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mb/google/hatch: Add mushu variant ......................................................................
Patch Set 6: Code-Review+1
(6 comments)
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... File src/mainboard/google/hatch/variants/mushu/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 11: [PchSerialIoIndexSPI1] = PchSerialIoPci,
Switched to mirror Hatch reference laptop.
Ack
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 26: RFU
Switched to mirror Hatch reference laptop.
Ack
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 27: PS175
Switched to mirror Hatch reference laptop.
Ack
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 28: MST
Switched to mirror Hatch reference laptop.
Ack
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 36: i2c[0]
Switched to mirror Hatch reference laptop.
Ack
https://review.coreboot.org/c/coreboot/+/37645/4/src/mainboard/google/hatch/... PS4, Line 41: .i2c[1]
Switched to mirror Hatch reference laptop.
Ack
Hello YH Lin, Rajat Jain, Angel Pons, Tim Wawrzynczak, Philip Chen, Bob Moragues, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37645
to look at the new patch set (#7).
Change subject: mb/google/hatch: Add mushu variant ......................................................................
mb/google/hatch: Add mushu variant
Create initial overlays and build for mushu
Signed-off-by: Bob Moragues moragues@chromium.org Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/mushu/Makefile.inc A src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/mushu/include/variant/ec.h A src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h A src/mainboard/google/hatch/variants/mushu/overridetree.cb 8 files changed, 345 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37645/7
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mb/google/hatch: Add mushu variant ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37645/7/src/mainboard/google/hatch/... File src/mainboard/google/hatch/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/37645/7/src/mainboard/google/hatch/... PS7, Line 44: BOARD_ROMSIZE_KB_32768 Is this accurate for Mushu? I know this is a copy of Hatch reference, but most boards based on Hatch have moved on to using 16MiB SPI flash. So, it would be good to confirm this.
https://review.coreboot.org/c/coreboot/+/37645/7/src/mainboard/google/hatch/... PS7, Line 45: ROMSTAGE_SPD_SMBUS This is not correct. Mushu would still use CBFS SPD.
Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mb/google/hatch: Add mushu variant ......................................................................
Patch Set 7:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37645/7/src/mainboard/google/hatch/... File src/mainboard/google/hatch/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/37645/7/src/mainboard/google/hatch/... PS7, Line 44: BOARD_ROMSIZE_KB_32768
Is this accurate for Mushu? I know this is a copy of Hatch reference, but most boards based on Hatch […]
The schematic still shows the 32MB part. They may be changing that. I will start an email thread on this.
https://review.coreboot.org/c/coreboot/+/37645/7/src/mainboard/google/hatch/... PS7, Line 45: ROMSTAGE_SPD_SMBUS
This is not correct. Mushu would still use CBFS SPD.
I double checked the Hatch reference board. It is still using ROMSTAGE_SPD_SMBUS. Has CBFS SPD been rolled out to all the hatch variants?
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mb/google/hatch: Add mushu variant ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37645/7/src/mainboard/google/hatch/... File src/mainboard/google/hatch/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/37645/7/src/mainboard/google/hatch/... PS7, Line 45: ROMSTAGE_SPD_SMBUS
I double checked the Hatch reference board. It is still using ROMSTAGE_SPD_SMBUS.
Hatch reference board never used ROMSTAGE_SPD_SMBUS.
The only variant that selects ROMSTAGE_SPD_SMBUS is Puff: https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/google/hatc...
and if ROMSTAGE_SPD_SMBUS is not selected, then ROMSTAGE_SPD_CBFS gets selected:
https://review.coreboot.org/cgit/coreboot.git/tree/src/mainboard/google/hatc...
Hello YH Lin, Rajat Jain, Angel Pons, Bob Moragues, Tim Wawrzynczak, Philip Chen, Shelley Chen, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37645
to look at the new patch set (#8).
Change subject: mb/google/hatch: Add mushu variant ......................................................................
mb/google/hatch: Add mushu variant
Create initial overlays and build for mushu
Signed-off-by: Bob Moragues moragues@chromium.org Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/mushu/Makefile.inc A src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/mushu/include/variant/ec.h A src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h A src/mainboard/google/hatch/variants/mushu/overridetree.cb 8 files changed, 344 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/37645/8
Bob Moragues has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mb/google/hatch: Add mushu variant ......................................................................
Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/37645/7/src/mainboard/google/hatch/... File src/mainboard/google/hatch/Kconfig.name:
https://review.coreboot.org/c/coreboot/+/37645/7/src/mainboard/google/hatch/... PS7, Line 44: BOARD_ROMSIZE_KB_32768
The schematic still shows the 32MB part. […]
Done
https://review.coreboot.org/c/coreboot/+/37645/7/src/mainboard/google/hatch/... PS7, Line 45: ROMSTAGE_SPD_SMBUS
I double checked the Hatch reference board. It is still using ROMSTAGE_SPD_SMBUS. […]
Done
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mb/google/hatch: Add mushu variant ......................................................................
Patch Set 8:
I think this look okay, just waiting for confirmation of ROM size
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mb/google/hatch: Add mushu variant ......................................................................
Patch Set 8: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/37645 )
Change subject: mb/google/hatch: Add mushu variant ......................................................................
mb/google/hatch: Add mushu variant
Create initial overlays and build for mushu
Signed-off-by: Bob Moragues moragues@chromium.org Change-Id: I81b5bf960ead0463159ac35f4f96e3ccc8c0364e Reviewed-on: https://review.coreboot.org/c/coreboot/+/37645 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/google/hatch/Kconfig M src/mainboard/google/hatch/Kconfig.name A src/mainboard/google/hatch/variants/mushu/Makefile.inc A src/mainboard/google/hatch/variants/mushu/gpio.c A src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl A src/mainboard/google/hatch/variants/mushu/include/variant/ec.h A src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h A src/mainboard/google/hatch/variants/mushu/overridetree.cb 8 files changed, 344 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index dff5273..90c5ed3 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -95,6 +95,7 @@ default "Jinlon" if BOARD_GOOGLE_JINLON default "Kindred" if BOARD_GOOGLE_KINDRED default "Kohaku" if BOARD_GOOGLE_KOHAKU + default "Mushu" if BOARD_GOOGLE_MUSHU default "Puff" if BOARD_GOOGLE_PUFF default "Stryke" if BOARD_GOOGLE_STRYKE
@@ -117,6 +118,7 @@ default "jinlon" if BOARD_GOOGLE_JINLON default "kindred" if BOARD_GOOGLE_KINDRED default "kohaku" if BOARD_GOOGLE_KOHAKU + default "mushu" if BOARD_GOOGLE_MUSHU default "puff" if BOARD_GOOGLE_PUFF default "stryke" if BOARD_GOOGLE_STRYKE
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name index ed90de6..e216135 100644 --- a/src/mainboard/google/hatch/Kconfig.name +++ b/src/mainboard/google/hatch/Kconfig.name @@ -38,6 +38,11 @@ select CHROMEOS_DSM_CALIB select DRIVERS_I2C_RT1011
+config BOARD_GOOGLE_MUSHU + bool "-> Mushu" + select BOARD_GOOGLE_BASEBOARD_HATCH + select BOARD_ROMSIZE_KB_16384 + config BOARD_GOOGLE_PUFF bool "-> Puff" select BOARD_GOOGLE_BASEBOARD_HATCH diff --git a/src/mainboard/google/hatch/variants/mushu/Makefile.inc b/src/mainboard/google/hatch/variants/mushu/Makefile.inc new file mode 100644 index 0000000..a990b5a --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/Makefile.inc @@ -0,0 +1,23 @@ +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 + +ramstage-y += gpio.c +bootblock-y += gpio.c diff --git a/src/mainboard/google/hatch/variants/mushu/gpio.c b/src/mainboard/google/hatch/variants/mushu/gpio.c new file mode 100644 index 0000000..56f587b --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/gpio.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <commonlib/helpers.h> + +static const struct pad_config gpio_table[] = { + /* C13 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_C13, UP_20K, PLTRST, LEVEL, INVERT)}; + +const struct pad_config *override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* + * GPIOs configured before ramstage + * Note: the Hatch platform's romstage will configure + * the MEM_STRAP_* (a.k.a GPIO_MEM_CONFIG_*) pins + * as inputs before it reads them, so they are not + * needed in this table. + */ +static const struct pad_config early_gpio_table[] = { + /* A12 : FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_A12, 0, DEEP), + /* B15 : H1_SLAVE_SPI_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : H1_SLAVE_SPI_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : H1_SLAVE_SPI_MISO_R */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : H1_SLAVE_SPI_MOSI_R */ + PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C14 : BT_DISABLE_L */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* PCH_WP_OD */ + PAD_CFG_GPI(GPP_C20, NONE, DEEP), + /* C21 : H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C23 : WLAN_PE_RST# */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + /* E1 : M2_SSD_PEDET */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + /* E5 : SATA_DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), + /* F2 : MEM_CH_SEL */ + PAD_CFG_GPI(GPP_F2, NONE, PLTRST), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..31f72b3 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/acpi/dptf.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h b/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h new file mode 100644 index 0000000..768987d --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h new file mode 100644 index 0000000..29e5904 --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/include/variant/gpio.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +/* Memory configuration board straps */ +#define GPIO_MEM_CONFIG_0 GPP_F20 +#define GPIO_MEM_CONFIG_1 GPP_F21 +#define GPIO_MEM_CONFIG_2 GPP_F11 +#define GPIO_MEM_CONFIG_3 GPP_F22 + +#endif diff --git a/src/mainboard/google/hatch/variants/mushu/overridetree.cb b/src/mainboard/google/hatch/variants/mushu/overridetree.cb new file mode 100644 index 0000000..75c14ef --- /dev/null +++ b/src/mainboard/google/hatch/variants/mushu/overridetree.cb @@ -0,0 +1,181 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # VR Slew rate setting + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRateForIa" = "2" + register "SlowSlewRateForGt" = "2" + register "SlowSlewRateForSa" = "2" + register "FastPkgCRampDisableIa" = "1" + register "FastPkgCRampDisableGt" = "1" + register "FastPkgCRampDisableSa" = "1" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| GSPI1 | FP MCU | + #| I2C0 | Touchpad | + #| I2C1 | Touch screen | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 50, + .fall_time_ns = 15, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 60, + .fall_time_ns = 25, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 150, + .fall_time_ns = 150, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 120, + .fall_time_ns = 120, + }, + }" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "vSD3_CD_B" + + device domain 0 on + device pci 15.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_A21_IRQ)" + register "wake" = "GPE0_DW0_21" + device i2c 15 on end + end + end # I2C #0 + device pci 15.1 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "reset_delay_ms" = "100" + register "reset_off_delay_ms" = "5" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C4)" + register "stop_off_delay_ms" = "5" + device i2c 49 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "120" + register "generic.reset_off_delay_ms" = "3" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end + chip drivers/generic/gpio_keys + register "name" = ""PENH"" + register "gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A8)" + register "key.wake" = "GPE0_DW0_08" + register "key.wakeup_event_action" = "EV_ACT_DEASSERTED" + register "key.dev_name" = ""EJCT"" + register "key.linux_code" = "SW_PEN_INSERTED" + register "key.linux_input_type" = "EV_SW" + register "key.label" = ""pen_eject"" + device generic 0 on end + end + end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 on + chip drivers/i2c/sx9310 + register "desc" = ""SAR Proximity Sensor"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_prox_ctrl0" = "0x10" + register "reg_prox_ctrl1" = "0x00" + register "reg_prox_ctrl2" = "0x84" + register "reg_prox_ctrl3" = "0x0e" + register "reg_prox_ctrl4" = "0x07" + register "reg_prox_ctrl5" = "0xc6" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0x0d" + register "reg_prox_ctrl8" = "0x8d" + register "reg_prox_ctrl9" = "0x43" + register "reg_prox_ctrl10" = "0x1f" + register "reg_prox_ctrl11" = "0x00" + register "reg_prox_ctrl12" = "0x00" + register "reg_prox_ctrl13" = "0x00" + register "reg_prox_ctrl14" = "0x00" + register "reg_prox_ctrl15" = "0x00" + register "reg_prox_ctrl16" = "0x00" + register "reg_prox_ctrl17" = "0x00" + register "reg_prox_ctrl18" = "0x00" + register "reg_prox_ctrl19" = "0x00" + register "reg_sar_ctrl0" = "0x50" + register "reg_sar_ctrl1" = "0x8a" + register "reg_sar_ctrl2" = "0x3c" + device i2c 28 on end + end + end # I2C #3 + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)" + register "property_count" = "1" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + end #I2C #4 + device pci 1e.3 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_A23_IRQ)" + register "wake" = "GPE0_DW0_23" + device spi 1 on end + end # FPMCU + end # GSPI #1 + end + +end
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Angel Pons (Code Review) -
Bob Moragues (Code Review)
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Furquan Shaikh (Code Review)
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Patrick Georgi (Code Review)
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Tim Wawrzynczak (Code Review)