Nicolas Boichat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47283 )
Change subject: WIP: mediatek/mt8192: spm: Add checks ......................................................................
WIP: mediatek/mt8192: spm: Add checks
16-byte alignement is critical for program section, so let's assume it also is for the data section (before we accidentally hit the issue again, which is very unlikely as the 21 bytes of data would need to stride over a 4kb boundary).
Also, add assertions to make sure the offsets are valid.
BUG=b:172177570 TEST=Asurada boots up to shell, suspend works
Signed-off-by: Nicolas Boichat drinkcat@chromium.org Change-Id: I1d0643368e4fb04e23b0fc1daef98f4b548dabc6 --- M 3rdparty/amd_blobs M 3rdparty/blobs M src/soc/mediatek/mt8192/spm.c 3 files changed, 17 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47283/1
diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 335f577..539d31a 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 335f577697f7d27353a84b8a156a67a1dbad255f +Subproject commit 539d31ab9ea89084fa5edf7cc9ac3122786d5454 diff --git a/3rdparty/blobs b/3rdparty/blobs index 0839a7c..5e8dd64 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 0839a7cb848f783b42aa133606c9e109174c4a55 +Subproject commit 5e8dd6456365461e725b53968ef8b82656d86560 diff --git a/src/soc/mediatek/mt8192/spm.c b/src/soc/mediatek/mt8192/spm.c index 4847377..b10268c 100644 --- a/src/soc/mediatek/mt8192/spm.c +++ b/src/soc/mediatek/mt8192/spm.c @@ -430,16 +430,22 @@ 0x1f17618b, 0x61acb7ed, 0x01a8f1a5, 0x1100040c, 0x00a041be, 0x48fc1f1f, 0x01a8f1a5, 0x1100040c, 0xf1a581b8, 0x000c01a8, 0x31be1120, 0x60ee1f1f, 0x01a8d1a5, 0x1140000c, 0x20688314, 0x0600800f, 0x07800000, 0xcfa58049, - 0x67670007, 0x3f20e74b, 0x01000100, 0x01000201, 0x02010201, 0x01000402, + 0x67670007, 0x3f20e74b, /* End of program */ + /* Padding to 16-byte alignment (14 bytes) */ + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, + /* Data */ + 0x01000100, 0x01000201, 0x02010201, 0x01000402, 0x02010402, 0x04020402, 0x01000803, 0x02010803, 0x04020803, 0x01001004, 0x02011004, 0x04021004, 0x08031004, 0x01002005, 0x02012005, 0x04022005, 0x08032005, 0x01004006, 0x02014006, 0x04024006, 0x08034006 };
-static struct spm_desc spm_firmware = { +static const struct spm_desc spm_firmware = { .version = "pcm_suspend_v1.45_20201028_mtcmosapi", - .pmem_words = 0x9c2, - .total_words = 0x9d7, + .pmem_words = 0x9d0, + .total_words = 0x9e5, .pmem_start = 0x10000000, .dmem_start = 0x10003800 }; @@ -937,6 +943,11 @@ pmem_start = spm_firmware.pmem_start; dmem_start = spm_firmware.dmem_start;
+ /* DMA needs 16-byte aligned source data. */ + assert((ptr % 16) == 0); + assert((pmem_words % 16) == 0); + assert(total_words == ARRAY_SIZE(spm_firmware_binary)); + /* tell IM where is PCM code (use slave mode if code existed) */ if (read32(&mtk_spm->md32pcm_dma0_src) != ptr || read32(&mtk_spm->md32pcm_dma0_dst) != pmem_start ||
Nicolas Boichat has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47283 )
Change subject: WIP: mediatek/mt8192: spm: Add checks ......................................................................
Patch Set 1:
Argh accidentally moved the blobs too ,-(
These changes may be necessary. Roger: Please help check with SPM designer.
Hello build bot (Jenkins), Roger Lu, Sj Huang, Yidi Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47283
to look at the new patch set (#2).
Change subject: WIP: mediatek/mt8192: spm: Add checks ......................................................................
WIP: mediatek/mt8192: spm: Add checks
16-byte alignement is critical for program section, so let's assume it also is for the data section (before we accidentally hit the issue again, which is very unlikely as the 21 bytes of data would need to stride over a 4kb boundary).
Also, add assertions to make sure the offsets are valid.
BUG=b:172177570 TEST=Asurada boots up to shell, suspend works
Signed-off-by: Nicolas Boichat drinkcat@chromium.org Change-Id: I1d0643368e4fb04e23b0fc1daef98f4b548dabc6 --- M 3rdparty/amd_blobs M 3rdparty/blobs M src/soc/mediatek/mt8192/spm.c 3 files changed, 7 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47283/2
Hello build bot (Jenkins), Roger Lu, Sj Huang, Yidi Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/47283
to look at the new patch set (#3).
Change subject: WIP: mediatek/mt8192: spm: Add checks ......................................................................
WIP: mediatek/mt8192: spm: Add checks
16-byte alignement is critical for program section, so let's assume it also is for the data section (before we accidentally hit the issue again, which is very unlikely as the 21 bytes of data would need to stride over a 4kb boundary).
BUG=b:172177570 TEST=Asurada boots up to shell, suspend works
Signed-off-by: Nicolas Boichat drinkcat@chromium.org Change-Id: I1d0643368e4fb04e23b0fc1daef98f4b548dabc6 --- M 3rdparty/amd_blobs M 3rdparty/blobs M src/soc/mediatek/mt8192/spm.c 3 files changed, 7 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/47283/3
Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47283 )
Change subject: WIP: mediatek/mt8192: spm: Add checks ......................................................................
Patch Set 3:
CB:46389 includes this change.
Nicolas Boichat has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/47283 )
Change subject: WIP: mediatek/mt8192: spm: Add checks ......................................................................
Abandoned
Thanks!
-
Nicolas Boichat (Code Review) -
Yidi Lin (Code Review)