Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47625 )
Change subject: nb/intel/sandybridge: Rename `timC_discovery` and related ......................................................................
nb/intel/sandybridge: Rename `timC_discovery` and related
This function simply determines the best delay for the TX DQ PIs.
Change-Id: If44c4f661d8c81fe41532ce2bfe3718392b9fe94 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 10 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/47625/1
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 664fef2..c495a8f 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1427,7 +1427,7 @@ return 0; }
-static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) +static void test_tx_dq(ramctr_timing *ctrl, int channel, int slotrank) { int lane;
@@ -1454,7 +1454,7 @@ wait_for_iosav(channel); }
-static void timC_threshold_process(int *data, const int count) +static void tx_dq_threshold_process(int *data, const int count) { int min = data[0]; int max = min; @@ -1473,9 +1473,9 @@ printram("threshold=%d min=%d max=%d\n", threshold, min, max); }
-static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) +static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank) { - int timC; + int tx_dq; int stats[NUM_LANES][MAX_TIMC + 1]; int lane;
@@ -1486,14 +1486,14 @@ /* Execute command queue */ iosav_run_once(channel);
- for (timC = 0; timC <= MAX_TIMC; timC++) { - FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; + for (tx_dq = 0; tx_dq <= MAX_TIMC; tx_dq++) { + FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = tx_dq; program_timings(ctrl, channel);
- test_timC(ctrl, channel, slotrank); + test_tx_dq(ctrl, channel, slotrank);
FOR_ALL_LANES { - stats[lane][timC] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); + stats[lane][tx_dq] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } FOR_ALL_LANES { @@ -1506,7 +1506,7 @@ * With command training not being done yet, the lane can be erroneous. * Take the average as reference and try again to find a run. */ - timC_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); + tx_dq_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane]));
if (rn.all || rn.length < 8) { @@ -1903,7 +1903,7 @@ }
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_timC(ctrl, channel, slotrank); + err = tx_dq_write_leveling(ctrl, channel, slotrank); if (err) return err; }
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47625 )
Change subject: nb/intel/sandybridge: Rename `timC_discovery` and related ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/47625 )
Change subject: nb/intel/sandybridge: Rename `timC_discovery` and related ......................................................................
nb/intel/sandybridge: Rename `timC_discovery` and related
This function simply determines the best delay for the TX DQ PIs.
Change-Id: If44c4f661d8c81fe41532ce2bfe3718392b9fe94 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/47625 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 10 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b58328b..d9c60e4 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1409,7 +1409,7 @@ return 0; }
-static void test_timC(ramctr_timing *ctrl, int channel, int slotrank) +static void test_tx_dq(ramctr_timing *ctrl, int channel, int slotrank) { int lane;
@@ -1528,7 +1528,7 @@ wait_for_iosav(channel); }
-static void timC_threshold_process(int *data, const int count) +static void tx_dq_threshold_process(int *data, const int count) { int min = data[0]; int max = min; @@ -1547,9 +1547,9 @@ printram("threshold=%d min=%d max=%d\n", threshold, min, max); }
-static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) +static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank) { - int timC; + int tx_dq; int stats[NUM_LANES][MAX_TIMC + 1]; int lane;
@@ -1560,14 +1560,14 @@ /* Execute command queue */ iosav_run_once(channel);
- for (timC = 0; timC <= MAX_TIMC; timC++) { - FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; + for (tx_dq = 0; tx_dq <= MAX_TIMC; tx_dq++) { + FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = tx_dq; program_timings(ctrl, channel);
- test_timC(ctrl, channel, slotrank); + test_tx_dq(ctrl, channel, slotrank);
FOR_ALL_LANES { - stats[lane][timC] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); + stats[lane][tx_dq] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } FOR_ALL_LANES { @@ -1580,7 +1580,7 @@ * With command training not being done yet, the lane can be erroneous. * Take the average as reference and try again to find a run. */ - timC_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); + tx_dq_threshold_process(stats[lane], ARRAY_SIZE(stats[lane])); rn = get_longest_zero_run(stats[lane], ARRAY_SIZE(stats[lane]));
if (rn.all || rn.length < 8) { @@ -2039,7 +2039,7 @@ }
FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_timC(ctrl, channel, slotrank); + err = tx_dq_write_leveling(ctrl, channel, slotrank); if (err) return err; }
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)