Attention is currently required from: Annie Chen, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Lean Sheng Tan, Nico Huber, Nill Ge, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu.
Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78327?usp=email )
Change subject: soc/intel/xeon_sp: Redesign resource allocation ......................................................................
Patch Set 17:
(5 comments)
Patchset:
PS17: Tested and revised for ArcherCity CRB (SPR-XCC)
P.S. SPR has different IOAT configs. SPR-XCC presents 3 accelerators per each IOAT stack. SPR-MCC presents 5 accelerators per each IOAT stack. Revised the codes to adapt both.
Points checked:
1. IOAT domains are created and scanned. 2. DPRs are configured for each IOAT domain. 3. IOAT resources are assigned by coreboot and reused by LinuxBoot.
Logs:
[0m[DEBUG] DOMAIN: 0000 enabled[0m [0m[DEBUG] DOMAIN: 0001 enabled[0m [0m[DEBUG] DOMAIN: 0002 enabled[0m [0m[DEBUG] DOMAIN: 0003 enabled[0m [0m[DEBUG] DOMAIN: 0120 enabled[0m [0m[DEBUG] DOMAIN: 0122 enabled[0m [0m[DEBUG] DOMAIN: 011f enabled[0m [0m[DEBUG] DOMAIN: 0125 enabled[0m [0m[DEBUG] DOMAIN: 0127 enabled[0m [0m[DEBUG] DOMAIN: 0124 enabled[0m [0m[DEBUG] DOMAIN: 012a enabled[0m [0m[DEBUG] DOMAIN: 012c enabled[0m [0m[DEBUG] DOMAIN: 0129 enabled[0m [0m[DEBUG] DOMAIN: 012f enabled[0m [0m[DEBUG] DOMAIN: 0131 enabled[0m [0m[DEBUG] DOMAIN: 012e enabled[0m
[0m[DEBUG] DOMAIN: 0120 scanning...[0m [0m[DEBUG] PCI: pci_scan_bus for bus e8[0m [0m[DEBUG] scan_bus: bus DOMAIN: 0120 finished in 4 msecs[0m [0m[DEBUG] DOMAIN: 0122 scanning...[0m [0m[DEBUG] PCI: pci_scan_bus for bus ea[0m [0m[DEBUG] scan_bus: bus DOMAIN: 0122 finished in 4 msecs[0m [0m[DEBUG] DOMAIN: 011f scanning...[0m [0m[DEBUG] PCI: pci_scan_bus for bus e7[0m [0m[SPEW ] PCI: e7:00.0 [8086/0000] ops[0m [0m[DEBUG] PCI: e7:00.0 [8086/09a2] enabled[0m [0m[DEBUG] PCI: e7:00.1 [8086/09a4] enabled[0m [0m[DEBUG] PCI: e7:00.2 [8086/09a3] enabled[0m [0m[DEBUG] PCI: e7:00.3 [8086/09a5] enabled[0m [0m[SPEW ] PCI: e7:00.4 [8086/0000] ops[0m [0m[DEBUG] PCI: e7:00.4 [8086/0b23] enabled[0m [0m[DEBUG] PCI: e7:01.0 [8086/0b25] enabled[0m [0m[DEBUG] PCI: e7:02.0 [8086/0cfe] enabled[0m [0m[DEBUG] PCI: e7:03.0 [8086/09a6] enabled[0m [0m[DEBUG] PCI: e7:03.1 [8086/09a7] enabled[0m [0m[DEBUG] PCI: e7:03.2 [8086/09a8] enabled[0m [0m[DEBUG] scan_bus: bus DOMAIN: 011f finished in 63 msecs[0m
[0m[DEBUG] DOMAIN: 0120[0m [0m[SPEW ] DOMAIN: 0120 resource base 0 size 0 align 0 gran 0 limit ffffffffffffffff flags 40000200 index 0[0m [0m[SPEW ] DOMAIN: 0120 resource base 204000000000 size 100000000 align 0 gran 0 limit 2040ffffffff flags 40000200 index 1[0m [0m[DEBUG] DOMAIN: 0122[0m [0m[SPEW ] DOMAIN: 0122 resource base 0 size 0 align 0 gran 0 limit ffffffffffffffff flags 40000200 index 0[0m [0m[SPEW ] DOMAIN: 0122 resource base 204100000000 size 400000000 align 0 gran 0 limit 2044ffffffff flags 40000200 index 1[0m [0m[DEBUG] DOMAIN: 011f child on link 0 PCI: e7:00.0[0m [0m[SPEW ] DOMAIN: 011f resource base f9800000 size 800000 align 0 gran 0 limit f9ffffff flags 40000200 index 0[0m [0m[SPEW ] DOMAIN: 011f resource base 204a00000000 size 600000000 align 0 gran 0 limit 204fffffffff flags 40000200 index 1[0m [0m[DEBUG] PCI: e7:00.0[0m [0m[DEBUG] PCI: e7:00.1[0m [0m[DEBUG] PCI: e7:00.2[0m [0m[DEBUG] PCI: e7:00.3[0m [0m[DEBUG] PCI: e7:00.4[0m [0m[DEBUG] PCI: e7:01.0[0m [0m[SPEW ] PCI: e7:01.0 resource base 204ffffb0000 size 10000 align 16 gran 16 limit 204ffffbffff flags 60001201 index 10[0m [0m[SPEW ] PCI: e7:01.0 resource base 204ffffe0000 size 20000 align 17 gran 17 limit 204fffffffff flags 60001201 index 18[0m [0m[DEBUG] PCI: e7:02.0[0m [0m[SPEW ] PCI: e7:02.0 resource base 204ffffa0000 size 10000 align 16 gran 16 limit 204ffffaffff flags 60001201 index 10[0m [0m[SPEW ] PCI: e7:02.0 resource base 204ffffc0000 size 20000 align 17 gran 17 limit 204ffffdffff flags 60001201 index 18[0m [0m[DEBUG] PCI: e7:03.0[0m [0m[SPEW ] PCI: e7:03.0 resource base f9f00000 size 100000 align 20 gran 20 limit f9ffffff flags 60000200 index 10[0m [0m[DEBUG] PCI: e7:03.1[0m [0m[SPEW ] PCI: e7:03.1 resource base f9dbe000 size 2000 align 13 gran 13 limit f9dbffff flags 60000200 index 10[0m [0m[SPEW ] PCI: e7:03.1 resource base f9dc0000 size 40000 align 18 gran 18 limit f9dfffff flags 60000200 index 14[0m [0m[DEBUG] PCI: e7:03.2[0m [0m[SPEW ] PCI: e7:03.2 resource base f9e00000 size 100000 align 20 gran 20 limit f9efffff flags 60000200 index 10[0m
[7m[ERROR] configure_dpr for PCI: e7:00.0[0m [0m[SPEW ] <null> read_resources bus 231 link: 0 done[0m [0m[SPEW ] <null> read_resources bus 237 link: 0[0m [0m[SPEW ] <null> read_resources bus 237 link: 0 done[0m [0m[SPEW ] <null> read_resources bus 239 link: 0[0m [0m[SPEW ] <null> read_resources bus 239 link: 0 done[0m [0m[SPEW ] <null> read_resources bus 236 link: 0[0m
PCI host bridge to bus 0000:e7 pci_bus 0000:e7: root bus resource [mem 0xf9800000-0xf9ffffff window] pci_bus 0000:e7: root bus resource [mem 0x204a00000000-0x204fffffffff window] pci_bus 0000:e7: root bus resource [bus e7] pci 0000:e7:00.0: [8086:09a2] type 00 class 0x088000 pci 0000:e7:00.1: [8086:09a4] type 00 class 0x088000 pci 0000:e7:00.2: [8086:09a3] type 00 class 0x088000 pci 0000:e7:00.3: [8086:09a5] type 00 class 0x088000 pci 0000:e7:00.4: [8086:0b23] type 00 class 0x080700 pci 0000:e7:01.0: [8086:0b25] type 00 class 0x088000 pci 0000:e7:01.0: reg 0x10: [mem 0x204ffffb0000-0x204ffffbffff 64bit pref] pci 0000:e7:01.0: reg 0x18: [mem 0x204ffffe0000-0x204fffffffff 64bit pref] pci 0000:e7:02.0: [8086:0cfe] type 00 class 0x088000 pci 0000:e7:02.0: reg 0x10: [mem 0x204ffffa0000-0x204ffffaffff 64bit pref] pci 0000:e7:02.0: reg 0x18: [mem 0x204ffffc0000-0x204ffffdffff 64bit pref] pci 0000:e7:03.0: [8086:09a6] type 00 class 0x088000 pci 0000:e7:03.0: reg 0x10: [mem 0xf9f00000-0xf9ffffff] pci 0000:e7:03.1: [8086:09a7] type 00 class 0x088000 pci 0000:e7:03.1: reg 0x10: [mem 0xf9dbe000-0xf9dbffff] pci 0000:e7:03.1: reg 0x14: [mem 0xf9dc0000-0xf9dfffff] pci 0000:e7:03.2: [8086:09a8] type 00 class 0x088000 pci 0000:e7:03.2: reg 0x10: [mem 0xf9e00000-0xf9efffff] ACPI: PCI Root Bridge [PM08] (domain 0000 [bus e8-e9]) acpi PNP0A08:07: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3] acpi PNP0A08:07: PCIe port services disabled; not requesting _OSC control PCI host bridge to bus 0000:e8 pci_bus 0000:e8: root bus resource [mem 0x204000000000-0x2040ffffffff window] pci_bus 0000:e8: root bus resource [bus e8-e9] ACPI: PCI Root Bridge [HQ08] (domain 0000 [bus ea-eb]) acpi PNP0A08:08: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3] acpi PNP0A08:08: PCIe port services disabled; not requesting _OSC control PCI host bridge to bus 0000:ea pci_bus 0000:ea: root bus resource [mem 0x204100000000-0x2044ffffffff window] pci_bus 0000:ea: root bus resource [bus ea-eb]
pci_bus 0000:e7: resource 4 [mem 0xf9800000-0xf9ffffff window] pci_bus 0000:e7: resource 5 [mem 0x204a00000000-0x204fffffffff window] pci_bus 0000:e8: resource 4 [mem 0x204000000000-0x2040ffffffff window] pci_bus 0000:ea: resource 4 [mem 0x204100000000-0x2044ffffffff window]
File src/soc/intel/xeon_sp/spr/ioat.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/4f2327a2_e1809bad : PS14, Line 73: const unsigned int domain_base = MAX_SOCKET * MAX_LOGIC_IIO_STACK;
I decided to simply add the bus number on top of this. We could also […]
From debug experience, using leading bus ID as domain ID would be more straightforward, which could be addressed in later patches. This patch is already quite large and let us merge it first if no opens :)
File src/soc/intel/xeon_sp/spr/ioat.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/77a08960_b5d627d5 : PS17, Line 50: bus->max_subordinate = bus_limit; each domain will own 2 busses instead of 1.
https://review.coreboot.org/c/coreboot/+/78327/comment/f0760eb4_f3df0282 : PS17, Line 109: create_ioat_domain(bus, domain_base, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit); Make CPM1 and HQM1 optional on 3 accelerator SKUs where smaller bus range is provided. P.S. Our test is fulfilled on 3 accelerator SKU.
File src/soc/intel/xeon_sp/spr/soc_acpi.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/e5b30708_e3a0a567 : PS17, Line 254: to review
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Shuo Liu (Code Review)