Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46700 )
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
soc/intel/broadwell: Separate PCH in devicetree
Given the huge number of interlinked parts, this change is rather noisy.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/pch.c A src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/systemagent.c 24 files changed, 437 insertions(+), 395 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46700/1
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index a309762..26a5336 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -15,27 +15,6 @@ # Set backlight PWM value for eDP register "gpu_pch_backlight_pwm_hz" = "200"
- # EC range is 0x800-0x9ff - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x00fc0901" - - # EC_SMI is GPIO34 - register "alt_gp_smi_en" = "0x0004" - register "gpe0_en_1" = "0x00000000" - # EC_SCI is GPIO36 - register "gpe0_en_2" = "0x00000010" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sio_acpi_mode" = "1" - - # Force enable ASPM for PCIe Port1 - register "pcie_port_force_aspm" = "0x01" - - # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013c0000" - register "s0ix_enable" = "1"
device cpu_cluster 0 on @@ -46,40 +25,64 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip ec/google/chromeec - device pnp 0c09.0 on end - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 off end # SMBus - device pci 1f.6 on end # Thermal + + chip soc/intel/broadwell/pch + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sio_acpi_mode" = "1" + + # Force enable ASPM for PCIe Port1 + register "pcie_port_force_aspm" = "0x01" + + # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013c0000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 off end # SMBus + device pci 1f.6 on end # Thermal + end end end diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index 60aef30..151c828 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -7,9 +7,11 @@ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
- # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on + chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + end + end end diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index da80fec..2958cd8 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -7,9 +7,11 @@ register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
- # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x7" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on + chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x7" + register "sata_port1_gen3_dtle" = "0x5" + end + end end diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index f148964..88778d2 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -7,32 +7,34 @@ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
- register "sata_devslp_disable" = "0x1" - - register "sio_i2c0_voltage" = "1" # 1.8V - register "sio_i2c1_voltage" = "0" # 3.3V - - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - # Force enable ASPM for PCIe Port 5 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - register "s0ix_enable" = "0"
device domain 0 on - device pci 13.0 on end # Smart Sound Audio DSP - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) - device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) - device pci 1f.3 on end # SMBus + chip soc/intel/broadwell/pch + register "sata_devslp_disable" = "0x1" + + register "sio_i2c0_voltage" = "1" # 1.8V + register "sio_i2c1_voltage" = "0" # 3.3V + + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + + # Force enable ASPM for PCIe Port 5 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device pci 13.0 on end # Smart Sound Audio DSP + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) + device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) + device pci 1f.3 on end # SMBus + end end end diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index 75c202d..77c5807 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -7,9 +7,11 @@ register "gpu_panel_power_backlight_on_delay" = "500" # 50ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
- # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on + chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + end + end end diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 60aef30..151c828 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -7,9 +7,11 @@ register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
- # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on + chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" + end + end end diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index c5d2747..3a429fb 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -10,30 +10,32 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
- register "sata_port0_gen3_tx" = "0x72" - - # Set I2C0 to 1.8V - register "sio_i2c0_voltage" = "1" - - # Force enable ASPM for PCIe Port 3 - register "pcie_port_force_aspm" = "0x04" - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013b0000" + register "vr_slow_ramp_rate_set" = "3" + register "vr_slow_ramp_rate_enable" = "1"
# Disable S0ix for now register "s0ix_enable" = "0"
- register "vr_slow_ramp_rate_set" = "3" - register "vr_slow_ramp_rate_enable" = "1" - device domain 0 on - device pci 13.0 on end # Smart Sound Audio DSP - device pci 15.3 on end # GSPI0 - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 on end # PCIe Port #3 - device pci 1d.0 off end # USB2 EHCI + chip soc/intel/broadwell/pch + register "sata_port0_gen3_tx" = "0x72" + + # Set I2C0 to 1.8V + register "sio_i2c0_voltage" = "1" + + # Force enable ASPM for PCIe Port 3 + register "pcie_port_force_aspm" = "0x04" + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013b0000" + + device pci 13.0 on end # Smart Sound Audio DSP + device pci 15.3 on end # GSPI0 + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 + device pci 1d.0 off end # USB2 EHCI + end end end diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index c4707e0..94fd804 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -9,27 +9,6 @@ # Enable HDMI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" - - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000000" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "0x1" - - # Force enable ASPM for PCIe Port 4 - register "pcie_port_force_aspm" = "0x10" - - # Enable port coalescing - register "pcie_port_coalesce" = "1" - - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" - device cpu_cluster 0 on device lapic 0 on end end @@ -38,78 +17,102 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip drivers/pc80/tpm - device pnp 0c31.0 on end - end - chip superio/ite/it8772f - # Skip keyboard init - register "skip_keyboard" = "1" - # Enable PECI on TMPIN3 - register "peci_tmpin" = "3" - # Disable use of TMPIN1 - register "tmpin1_mode" = "0" - # Enable Thermal Diode on TMPIN2 - register "tmpin2_mode" = "1" - # Enable FAN2 - register "fan2_enable" = "1" - # Default FAN2 speed - register "fan2_speed" = "0x4d"
- device pnp 2e.0 off end # FDC - device pnp 2e.1 on # Serial Port 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + chip soc/intel/broadwell/pch + # SuperIO range is 0x700-0x73f + register "gen2_dec" = "0x003c0701" + + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000000" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sata_devslp_disable" = "0x1" + + # Force enable ASPM for PCIe Port 4 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end end - device pnp 2e.4 on # Environment Controller - io 0x60 = 0x700 - io 0x62 = 0x710 - irq 0x70 = 0x09 - irq 0xf2 = 0x20 - irq 0xf4 = 0x0 - irq 0xfa = 0x12 + chip superio/ite/it8772f + # Skip keyboard init + register "skip_keyboard" = "1" + # Enable PECI on TMPIN3 + register "peci_tmpin" = "3" + # Disable use of TMPIN1 + register "tmpin1_mode" = "0" + # Enable Thermal Diode on TMPIN2 + register "tmpin2_mode" = "1" + # Enable FAN2 + register "fan2_enable" = "1" + # Default FAN2 speed + register "fan2_speed" = "0x4d" + + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x700 + io 0x62 = 0x710 + irq 0x70 = 0x09 + irq 0xf2 = 0x20 + irq 0xf4 = 0x0 + irq 0xfa = 0x12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x720 + io 0x62 = 0x730 + end + device pnp 2e.5 off + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end # Keyboard + device pnp 2e.6 off + irq 0x70 = 12 + end # Mouse + device pnp 2e.a off end # IR end - device pnp 2e.7 on # GPIO - io 0x60 = 0x720 - io 0x62 = 0x730 - end - device pnp 2e.5 off - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end # Keyboard - device pnp 2e.6 off - irq 0x70 = 12 - end # Mouse - device pnp 2e.a off end # IR - end - end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end end end diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index bff39b7..29041aa 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -9,15 +9,6 @@ # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06"
- register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000400" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "sata_port_map" = "0x2" - register "sio_acpi_mode" = "1" - device cpu_cluster 0 on device lapic 0 on end end @@ -25,33 +16,45 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal + + chip soc/intel/broadwell/pch + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000400" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x2" + register "sio_acpi_mode" = "1" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end end end diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index b7c6fe5..0d0fc72 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -16,10 +16,6 @@ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
- # EC host command ranges are in 0x380-0x383 & 0x80-0x8f - register "gen1_dec" = "0x00000381" - register "gen2_dec" = "0x000c0081" - device cpu_cluster 0 on device lapic 0 on end end @@ -27,33 +23,40 @@ device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio - device pci 13.0 off end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 off end # Serial I/O DMA - device pci 15.1 off end # I2C0 - device pci 15.2 off end # I2C1 - device pci 15.3 off end # GSPI0 - device pci 15.4 off end # GSPI1 - device pci 15.5 off end # UART0 - device pci 15.6 off end # UART1 - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 off end # SDIO - device pci 19.0 off end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - LAN - device pci 1c.3 on end # PCIe Port #4 - WiFi - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe - device pci 1d.0 off end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 off end # Thermal + + chip soc/intel/broadwell/pch + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f + register "gen1_dec" = "0x00000381" + register "gen2_dec" = "0x000c0081" + + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 - LAN + device pci 1c.3 on end # PCIe Port #4 - WiFi + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 off end # Thermal + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index d3d0ae7..256077c 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell
- # Port 0 is HDD - # Port 3 is M.2 NGFF - register "sata_port_map" = "0x9" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "9" - register "sata_port3_gen3_dtle" = "9" - device domain 0 on - device pci 1c.2 on end # PCIe Port #3 - LAN + chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 3 is M.2 NGFF + register "sata_port_map" = "0x9" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "9" + register "sata_port3_gen3_dtle" = "9" + + device pci 1c.2 on end # PCIe Port #3 - LAN + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index c0c8d03..d88c19c 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,14 +1,16 @@ chip soc/intel/broadwell
- # Port 0 is HDD - # Port 1 is M.2 NGFF - register "sata_port_map" = "0x3" - - # Port tuning for link stability - register "sata_port0_gen3_dtle" = "7" - register "sata_port1_gen3_dtle" = "9" - device domain 0 on - device pci 1d.0 on end # USB2 EHCI + chip soc/intel/broadwell/pch + # Port 0 is HDD + # Port 1 is M.2 NGFF + register "sata_port_map" = "0x3" + + # Port tuning for link stability + register "sata_port0_gen3_dtle" = "7" + register "sata_port1_gen3_dtle" = "9" + + device pci 1d.0 on end # USB2 EHCI + end end end diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 220ad6f..06dd38b 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -14,11 +14,11 @@ #include <soc/pch.h> #include <soc/ramstage.h> #include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h>
static void adsp_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); struct resource *bar0, *bar1; u32 tmp32;
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 45d512a..81c9780 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -7,70 +7,6 @@ #include <stdint.h>
struct soc_intel_broadwell_config { - /* GPE configuration */ - uint32_t gpe0_en_1; - uint32_t gpe0_en_2; - uint32_t gpe0_en_3; - uint32_t gpe0_en_4; - - /* GPIO SMI configuration */ - uint32_t alt_gp_smi_en; - - /* IDE configuration */ - uint8_t sata_port_map; - uint32_t sata_port0_gen3_tx; - uint32_t sata_port1_gen3_tx; - uint32_t sata_port2_gen3_tx; - uint32_t sata_port3_gen3_tx; - uint32_t sata_port0_gen3_dtle; - uint32_t sata_port1_gen3_dtle; - uint32_t sata_port2_gen3_dtle; - uint32_t sata_port3_gen3_dtle; - - /* - * SATA DEVSLP Mux - * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 - * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 - */ - uint8_t sata_devslp_mux; - - /* - * DEVSLP Disable - * 0: DEVSLP is enabled - * 1: DEVSLP is disabled - */ - uint8_t sata_devslp_disable; - - /* Generic IO decode ranges */ - uint32_t gen1_dec; - uint32_t gen2_dec; - uint32_t gen3_dec; - uint32_t gen4_dec; - - /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; - - /* Force root port ASPM configuration with port bitmap */ - uint8_t pcie_port_force_aspm; - - /* Put SerialIO devices into ACPI mode instead of a PCI device */ - uint8_t sio_acpi_mode; - - /* I2C voltage select: 0=3.3V 1=1.8V */ - uint8_t sio_i2c0_voltage; - uint8_t sio_i2c1_voltage; - - /* Enable ADSP power gating features */ - uint8_t adsp_d3_pg_enable; - uint8_t adsp_sram_pg_enable; - - /* - * Clock Disable Map: - * [21:16] = CLKOUT_PCIE# 5-0 - * [24] = CLKOUT_ITPXDP - */ - uint32_t icc_clock_disable; - /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -107,9 +43,6 @@
struct i915_gpu_controller_info gfx;
- /* Enable S0iX support */ - int s0ix_enable; - /* * Minimum voltage for C6/C7 state: * 0x67 = 1.6V (full swing) @@ -132,9 +65,8 @@ /* Enable slow VR ramp rate */ int vr_slow_ramp_rate_enable;
- /* Deep SX enable */ - int deep_sx_enable_ac; - int deep_sx_enable_dc; + /* Enable S0iX support */ + int s0ix_enable;
/* TCC activation offset */ uint32_t tcc_offset; diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index 0b6ef0d..5d7eceb 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -8,7 +8,6 @@
void broadwell_init_pre_device(void *chip_info); void broadwell_init_cpus(struct device *dev); -void broadwell_pch_enable_dev(struct device *dev);
#if CONFIG(HAVE_REFCODE_BLOB) void broadwell_run_reference_code(void); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index dd4e15c..13ffd43 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -25,7 +25,7 @@ #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h> #include <acpi/acpigen.h> #include <southbridge/intel/common/rtc.h>
@@ -131,7 +131,7 @@ u16 reg16; const char *state; /* Get the chip configuration */ - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
/* Which state do we want to goto after g3 (power restored)? @@ -337,7 +337,7 @@
static void pch_init_deep_sx(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev);
if (config->deep_sx_enable_ac) { RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC); @@ -568,7 +568,7 @@ static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev);
/* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 80ffe2b..40a81d8 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -26,7 +26,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h>
#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> @@ -950,7 +950,7 @@ /* Check whether ME is present and do basic init */ static void intel_me_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; int mbp_ret; diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 2a27d92..e0c5bb0 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -166,10 +166,16 @@ } }
-void broadwell_pch_enable_dev(struct device *dev) +static void broadwell_pch_enable_dev(struct device *dev) { u16 reg16;
+ if (dev->path.type != DEVICE_PATH_PCI) + return; + + if (dev->ops && dev->ops->enable) + return; + /* These devices need special enable/disable handling */ switch (PCI_SLOT(dev->path.pci.devfn)) { case PCH_DEV_SLOT_PCIE: @@ -195,4 +201,9 @@ } }
+struct chip_operations soc_intel_broadwell_pch_ops = { + CHIP_NAME("Intel Broadwell PCH") + .enable_dev = &broadwell_pch_enable_dev, +}; + #endif diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/soc/intel/broadwell/pch/chip.h new file mode 100644 index 0000000..2164a31 --- /dev/null +++ b/src/soc/intel/broadwell/pch/chip.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_BROADWELL_PCH_CHIP_H_ +#define _SOC_INTEL_BROADWELL_PCH_CHIP_H_ + +#include <stdint.h> + +struct soc_intel_broadwell_pch_config { + /* GPE configuration */ + uint32_t gpe0_en_1; + uint32_t gpe0_en_2; + uint32_t gpe0_en_3; + uint32_t gpe0_en_4; + + /* GPIO SMI configuration */ + uint32_t alt_gp_smi_en; + + /* IDE configuration */ + uint8_t sata_port_map; + uint32_t sata_port0_gen3_tx; + uint32_t sata_port1_gen3_tx; + uint32_t sata_port2_gen3_tx; + uint32_t sata_port3_gen3_tx; + uint32_t sata_port0_gen3_dtle; + uint32_t sata_port1_gen3_dtle; + uint32_t sata_port2_gen3_dtle; + uint32_t sata_port3_gen3_dtle; + + /* + * SATA DEVSLP Mux + * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 + * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 + */ + uint8_t sata_devslp_mux; + + /* + * DEVSLP Disable + * 0: DEVSLP is enabled + * 1: DEVSLP is disabled + */ + uint8_t sata_devslp_disable; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable linear PCIe Root Port function numbers starting at zero */ + uint8_t pcie_port_coalesce; + + /* Force root port ASPM configuration with port bitmap */ + uint8_t pcie_port_force_aspm; + + /* Put SerialIO devices into ACPI mode instead of a PCI device */ + uint8_t sio_acpi_mode; + + /* I2C voltage select: 0=3.3V 1=1.8V */ + uint8_t sio_i2c0_voltage; + uint8_t sio_i2c1_voltage; + + /* Enable ADSP power gating features */ + uint8_t adsp_d3_pg_enable; + uint8_t adsp_sram_pg_enable; + + /* + * Clock Disable Map: + * [21:16] = CLKOUT_PCIE# 5-0 + * [24] = CLKOUT_ITPXDP + */ + uint32_t icc_clock_disable; + + /* Deep SX enable */ + int deep_sx_enable_ac; + int deep_sx_enable_dc; +}; + +#endif diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 0d41d42..c98201e 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -13,7 +13,7 @@ #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h> #include <soc/cpu.h> #include <delay.h>
@@ -121,7 +121,7 @@ root_port_config_update_gbe_port();
pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); rpc.coalesce = config->pcie_port_coalesce; }
@@ -436,7 +436,7 @@
static void pch_pcie_early(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); int do_aspm = 0; int rp = root_port_number(dev);
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index d68e17e..149dda1 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -12,7 +12,7 @@ #include <soc/rcba.h> #include <soc/romstage.h> #include <soc/smbus.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h>
static void pch_route_interrupts(void) { @@ -52,9 +52,9 @@ static void pch_enable_lpc(void) { /* Lookup device tree in romstage */ - const config_t *config; + const struct device *const dev = pcidev_on_root(0x1f, 0);
- config = config_of_soc(); + const struct soc_intel_broadwell_pch_config *config = config_of(dev);
pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index c9168325..b496e53 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -11,7 +11,7 @@ #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/sata.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h>
static inline u32 sir_read(struct device *dev, int idx) { @@ -27,7 +27,7 @@
static void sata_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); u32 reg32; u8 *abar; u16 reg16; @@ -256,7 +256,7 @@ static void sata_enable(struct device *dev) { /* Get the chip configuration */ - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); u16 map = 0x0060;
map |= (config->sata_port_map ^ 0xf) << 8; diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 766f5dd..d32a27d 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -14,7 +14,7 @@ #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/serialio.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h>
/* Set D3Hot Power State in ACPI mode */ static void serialio_enable_d3hot(struct resource *res) @@ -156,7 +156,7 @@
static void serialio_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1;
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 4b4848b..80b9939 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -475,12 +475,6 @@ dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; - } else if (dev->path.type == DEVICE_PATH_PCI) { - /* Handle PCH device enable */ - if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD && - (dev->ops == NULL || dev->ops->enable == NULL)) { - broadwell_pch_enable_dev(dev); - } } }
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46700 )
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
Patch Set 2: Code-Review-1
Moving around the devicetrees can be done reproducibly
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46700
to look at the new patch set (#3).
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
soc/intel/broadwell: Separate PCH in devicetree
Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/pch.c A src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/systemagent.c 24 files changed, 135 insertions(+), 121 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46700/3
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46700
to look at the new patch set (#4).
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
soc/intel/broadwell: Separate PCH in devicetree
Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/pch.c A src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/systemagent.c 24 files changed, 135 insertions(+), 121 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46700/4
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46700
to look at the new patch set (#6).
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
soc/intel/broadwell: Separate PCH in devicetree
Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/pch.c A src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/systemagent.c 24 files changed, 135 insertions(+), 121 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46700/6
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46700
to look at the new patch set (#7).
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
soc/intel/broadwell: Separate PCH in devicetree
Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/pch.c A src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/systemagent.c 24 files changed, 135 insertions(+), 121 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46700/7
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46700
to look at the new patch set (#9).
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
soc/intel/broadwell: Separate PCH in devicetree
Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/pch.c A src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/systemagent.c 24 files changed, 135 insertions(+), 121 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46700/9
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46700 )
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
Patch Set 9: Code-Review-2
Breaks booting on out-of-tree board:
CPU PL1 = 1542 Watts CPU PL2 = 1542 Watts CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:78f8607e - Halting Code: 0 eflags: 00010002 cr2: 00000000 eax: 00ddb030 ebx: 0000065c ecx: 0000065c edx: 0001b030 edi: 0001b030 esi: 78fb7000 ebp: 000007d0 esp: 78fc1ed0
0x78f86038: ff 7f 00 00 81 cf 00 80 0x78f86040: 01 00 50 68 80 c7 fa 78 0x78f86048: 6a 06 e8 69 d0 01 00 89 0x78f86050: fa b9 10 06 00 00 89 e8 0x78f86058: 0f 30 0f b7 6e 04 81 cb 0x78f86060: 00 00 01 00 83 c4 10 89 0x78f86068: 1d a0 59 d1 fe 89 3d a4 0x78f86070: 59 d1 fe 85 ed 74 38 bb 0x78f86078: 5c 06 00 00 89 d9 0f 32 0x78f86080: 51 89 c7 55 68 94 c7 fa 0x78f86088: 78 6a 06 e8 28 d0 01 00 0x78f86090: 8a 4c 24 10 89 f8 0f b7 0x78f86098: 56 04 d3 e2 89 d9 81 e2 0x78f860a0: ff 7f 00 00 81 ca 00 80 0x78f860a8: 01 00 0f 30 83 c4 10 0f 0x78f860b0: b7 7e 06 85 ff 74 55 bb 0x78fc1f4c: 0x78f9bf90 0x78fc1f48: 0x78fb6e44 0x78fc1f44: 0x78fb8320 0x78fc1f40: 0x00000075 0x78fc1f3c: 0x0002affc 0x78fc1f38: 0x0002affc 0x78fc1f34: 0x0002affc 0x78fc1f30: 0x00000075 0x78fc1f2c: 0x78fa2fbc 0x78fc1f28: 0x78fc8c20 0x78fc1f24: 0x78fb1c1e 0x78fc1f20: 0x78fb8320 0x78fc1f1c: 0x78f9bf27 0x78fc1f18: 0x78fc1fd8 0x78fc1f14: 0x00000005 0x78fc1f10: 0x78fb6e44 0x78fc1f0c: 0x78fb8320 0x78fc1f08: 0x78fb8320 0x78fc1f04: 0x78fb7000 0x78fc1f00: 0x0000001c 0x78fc1efc: 0x78f8c40f 0x78fc1ef8: 0x78fc1fd8 0x78fc1ef4: 0x00000005 0x78fc1ef0: 0x78fb6e44 0x78fc1eec: 0x78fb8320 0x78fc1ee8: 0x00000000 0x78fc1ee4: 0x00000000 0x78fc1ee0: 0x78fb6e40 0x78fc1edc: 0x00000000 0x78fc1ed8: 0x00000000 0x78fc1ed4: 0x00000008 0x78fc1ed0: 0x00000003 <-esp
Angel Pons has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/46700 )
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
Removed Code-Review-2 by Angel Pons th3fanbus@gmail.com
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46700 )
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
Patch Set 10:
Patch Set 9: Code-Review-2
Breaks booting on out-of-tree board:
CPU PL1 = 1542 Watts CPU PL2 = 1542 Watts CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:78f8607e - Halting Code: 0 eflags: 00010002 cr2: 00000000 eax: 00ddb030 ebx: 0000065c ecx: 0000065c edx: 0001b030 edi: 0001b030 esi: 78fb7000 ebp: 000007d0 esp: 78fc1ed0
CB:45011 fixes the problem.
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46700
to look at the new patch set (#12).
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
soc/intel/broadwell: Separate PCH in devicetree
Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes.
Tested on out-of-tree Acer Aspire E5-573, still boots.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/pch.c A src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/systemagent.c 24 files changed, 135 insertions(+), 121 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46700/12
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46700
to look at the new patch set (#14).
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
soc/intel/broadwell: Separate PCH in devicetree
Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes.
Tested on out-of-tree Acer Aspire E5-573, still boots.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/pch.c A src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/systemagent.c 24 files changed, 135 insertions(+), 121 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46700/14
Hello build bot (Jenkins), Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/46700
to look at the new patch set (#15).
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
soc/intel/broadwell: Separate PCH in devicetree
Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes.
Tested on out-of-tree Acer Aspire E5-573, still boots.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/pch.c A src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/systemagent.c 24 files changed, 135 insertions(+), 121 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/46700/15
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46700 )
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
Patch Set 18: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46700 )
Change subject: soc/intel/broadwell: Separate PCH in devicetree ......................................................................
soc/intel/broadwell: Separate PCH in devicetree
Flesh out the PCH configuration into a separate chip. Keep it within the Broadwell SoC directory for now, to ease moving files around. The boards were prepared beforehand and the devicetrees require next to no changes.
Tested on out-of-tree Acer Aspire E5-573, still boots.
Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700 Reviewed-by: Arthur Heymans arthur@aheymans.xyz Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/google/auron/devicetree.cb M src/mainboard/google/auron/variants/auron_paine/overridetree.cb M src/mainboard/google/auron/variants/auron_yuna/overridetree.cb M src/mainboard/google/auron/variants/buddy/overridetree.cb M src/mainboard/google/auron/variants/gandof/overridetree.cb M src/mainboard/google/auron/variants/lulu/overridetree.cb M src/mainboard/google/auron/variants/samus/overridetree.cb M src/mainboard/google/jecht/devicetree.cb M src/mainboard/intel/wtm2/devicetree.cb M src/mainboard/purism/librem_bdw/devicetree.cb M src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb M src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/include/soc/ramstage.h M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/me.c M src/soc/intel/broadwell/pch.c A src/soc/intel/broadwell/pch/chip.h M src/soc/intel/broadwell/pcie.c M src/soc/intel/broadwell/romstage/pch.c M src/soc/intel/broadwell/sata.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/systemagent.c 24 files changed, 135 insertions(+), 121 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 09593b7..26a5336 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -26,7 +26,7 @@ device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio
-# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # EC range is 0x800-0x9ff register "gen1_dec" = "0x00fc0801" register "gen2_dec" = "0x00fc0901" @@ -83,6 +83,6 @@ device pci 1f.2 on end # SATA Controller device pci 1f.3 off end # SMBus device pci 1f.6 on end # Thermal -# end + end end end diff --git a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb index f5f3eea..8111040 100644 --- a/src/mainboard/google/auron/variants/auron_paine/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/overridetree.cb @@ -8,12 +8,12 @@ register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5"
device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb index 5a64648..eb33d43 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/overridetree.cb @@ -8,12 +8,12 @@ register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x7" register "sata_port1_gen3_dtle" = "0x5"
device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index 5b6ab9f..60fb08c 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -10,7 +10,7 @@ register "s0ix_enable" = "0"
device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch register "sata_devslp_disable" = "0x1"
register "sio_i2c0_voltage" = "1" # 1.8V @@ -36,6 +36,6 @@ device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus -# end + end end end diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index 924e7d3..c7e2421 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -8,12 +8,12 @@ register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5"
device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index f5f3eea..8111040 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -8,12 +8,12 @@ register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5"
device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 9344575..d8aec0a 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -17,7 +17,7 @@ register "s0ix_enable" = "0"
device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch register "sata_port0_gen3_tx" = "0x72"
# Set I2C0 to 1.8V @@ -37,6 +37,6 @@ device pci 1c.2 on end # PCIe Port #3 device pci 1d.0 off end # USB2 EHCI device pci 1f.2 on end # SATA Controller -# end + end end end diff --git a/src/mainboard/google/jecht/devicetree.cb b/src/mainboard/google/jecht/devicetree.cb index e550822..94fd804 100644 --- a/src/mainboard/google/jecht/devicetree.cb +++ b/src/mainboard/google/jecht/devicetree.cb @@ -18,7 +18,7 @@ device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio
-# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701"
@@ -113,6 +113,6 @@ device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus device pci 1f.6 on end # Thermal -# end + end end end diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 927a603..29041aa 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -17,7 +17,7 @@ device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio
-# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x00000400" register "gpe0_en_2" = "0x00000000" @@ -55,6 +55,6 @@ device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus device pci 1f.6 on end # Thermal -# end + end end end diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 4f34f7d..0d0fc72 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -24,7 +24,7 @@ device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio
-# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # EC host command ranges are in 0x380-0x383 & 0x80-0x8f register "gen1_dec" = "0x00000381" register "gen2_dec" = "0x000c0081" @@ -57,6 +57,6 @@ device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus device pci 1f.6 off end # Thermal -# end + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb index 237e697..256077c 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell
device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # Port 0 is HDD # Port 3 is M.2 NGFF register "sata_port_map" = "0x9" @@ -11,6 +11,6 @@ register "sata_port3_gen3_dtle" = "9"
device pci 1c.2 on end # PCIe Port #3 - LAN -# end + end end end diff --git a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb index b9b29cd..d88c19c 100644 --- a/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb +++ b/src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb @@ -1,7 +1,7 @@ chip soc/intel/broadwell
device domain 0 on -# chip soc/intel/broadwell/pch + chip soc/intel/broadwell/pch # Port 0 is HDD # Port 1 is M.2 NGFF register "sata_port_map" = "0x3" @@ -11,6 +11,6 @@ register "sata_port1_gen3_dtle" = "9"
device pci 1d.0 on end # USB2 EHCI -# end + end end end diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index 220ad6f..06dd38b 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -14,11 +14,11 @@ #include <soc/pch.h> #include <soc/ramstage.h> #include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h>
static void adsp_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); struct resource *bar0, *bar1; u32 tmp32;
diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 45d512a..81c9780 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -7,70 +7,6 @@ #include <stdint.h>
struct soc_intel_broadwell_config { - /* GPE configuration */ - uint32_t gpe0_en_1; - uint32_t gpe0_en_2; - uint32_t gpe0_en_3; - uint32_t gpe0_en_4; - - /* GPIO SMI configuration */ - uint32_t alt_gp_smi_en; - - /* IDE configuration */ - uint8_t sata_port_map; - uint32_t sata_port0_gen3_tx; - uint32_t sata_port1_gen3_tx; - uint32_t sata_port2_gen3_tx; - uint32_t sata_port3_gen3_tx; - uint32_t sata_port0_gen3_dtle; - uint32_t sata_port1_gen3_dtle; - uint32_t sata_port2_gen3_dtle; - uint32_t sata_port3_gen3_dtle; - - /* - * SATA DEVSLP Mux - * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 - * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 - */ - uint8_t sata_devslp_mux; - - /* - * DEVSLP Disable - * 0: DEVSLP is enabled - * 1: DEVSLP is disabled - */ - uint8_t sata_devslp_disable; - - /* Generic IO decode ranges */ - uint32_t gen1_dec; - uint32_t gen2_dec; - uint32_t gen3_dec; - uint32_t gen4_dec; - - /* Enable linear PCIe Root Port function numbers starting at zero */ - uint8_t pcie_port_coalesce; - - /* Force root port ASPM configuration with port bitmap */ - uint8_t pcie_port_force_aspm; - - /* Put SerialIO devices into ACPI mode instead of a PCI device */ - uint8_t sio_acpi_mode; - - /* I2C voltage select: 0=3.3V 1=1.8V */ - uint8_t sio_i2c0_voltage; - uint8_t sio_i2c1_voltage; - - /* Enable ADSP power gating features */ - uint8_t adsp_d3_pg_enable; - uint8_t adsp_sram_pg_enable; - - /* - * Clock Disable Map: - * [21:16] = CLKOUT_PCIE# 5-0 - * [24] = CLKOUT_ITPXDP - */ - uint32_t icc_clock_disable; - /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse @@ -107,9 +43,6 @@
struct i915_gpu_controller_info gfx;
- /* Enable S0iX support */ - int s0ix_enable; - /* * Minimum voltage for C6/C7 state: * 0x67 = 1.6V (full swing) @@ -132,9 +65,8 @@ /* Enable slow VR ramp rate */ int vr_slow_ramp_rate_enable;
- /* Deep SX enable */ - int deep_sx_enable_ac; - int deep_sx_enable_dc; + /* Enable S0iX support */ + int s0ix_enable;
/* TCC activation offset */ uint32_t tcc_offset; diff --git a/src/soc/intel/broadwell/include/soc/ramstage.h b/src/soc/intel/broadwell/include/soc/ramstage.h index 0b6ef0d..5d7eceb 100644 --- a/src/soc/intel/broadwell/include/soc/ramstage.h +++ b/src/soc/intel/broadwell/include/soc/ramstage.h @@ -8,7 +8,6 @@
void broadwell_init_pre_device(void *chip_info); void broadwell_init_cpus(struct device *dev); -void broadwell_pch_enable_dev(struct device *dev);
#if CONFIG(HAVE_REFCODE_BLOB) void broadwell_run_reference_code(void); diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index 8b85a04..2111913 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -24,7 +24,7 @@ #include <soc/pm.h> #include <soc/ramstage.h> #include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h> #include <acpi/acpigen.h> #include <southbridge/intel/common/rtc.h>
@@ -130,7 +130,7 @@ u16 reg16; const char *state; /* Get the chip configuration */ - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
/* Which state do we want to goto after g3 (power restored)? @@ -336,7 +336,7 @@
static void pch_init_deep_sx(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev);
if (config->deep_sx_enable_ac) { RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC); @@ -567,7 +567,7 @@ static void pch_lpc_add_io_resources(struct device *dev) { struct resource *res; - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev);
/* Add the default claimed IO range for the LPC device. */ res = new_resource(dev, 0); diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 80ffe2b..40a81d8 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -26,7 +26,7 @@ #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h>
#if CONFIG(CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> @@ -950,7 +950,7 @@ /* Check whether ME is present and do basic init */ static void intel_me_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); me_bios_path path = intel_me_path(dev); me_bios_payload mbp_data; int mbp_ret; diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 2a27d92..e0c5bb0 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -166,10 +166,16 @@ } }
-void broadwell_pch_enable_dev(struct device *dev) +static void broadwell_pch_enable_dev(struct device *dev) { u16 reg16;
+ if (dev->path.type != DEVICE_PATH_PCI) + return; + + if (dev->ops && dev->ops->enable) + return; + /* These devices need special enable/disable handling */ switch (PCI_SLOT(dev->path.pci.devfn)) { case PCH_DEV_SLOT_PCIE: @@ -195,4 +201,9 @@ } }
+struct chip_operations soc_intel_broadwell_pch_ops = { + CHIP_NAME("Intel Broadwell PCH") + .enable_dev = &broadwell_pch_enable_dev, +}; + #endif diff --git a/src/soc/intel/broadwell/pch/chip.h b/src/soc/intel/broadwell/pch/chip.h new file mode 100644 index 0000000..2164a31 --- /dev/null +++ b/src/soc/intel/broadwell/pch/chip.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_INTEL_BROADWELL_PCH_CHIP_H_ +#define _SOC_INTEL_BROADWELL_PCH_CHIP_H_ + +#include <stdint.h> + +struct soc_intel_broadwell_pch_config { + /* GPE configuration */ + uint32_t gpe0_en_1; + uint32_t gpe0_en_2; + uint32_t gpe0_en_3; + uint32_t gpe0_en_4; + + /* GPIO SMI configuration */ + uint32_t alt_gp_smi_en; + + /* IDE configuration */ + uint8_t sata_port_map; + uint32_t sata_port0_gen3_tx; + uint32_t sata_port1_gen3_tx; + uint32_t sata_port2_gen3_tx; + uint32_t sata_port3_gen3_tx; + uint32_t sata_port0_gen3_dtle; + uint32_t sata_port1_gen3_dtle; + uint32_t sata_port2_gen3_dtle; + uint32_t sata_port3_gen3_dtle; + + /* + * SATA DEVSLP Mux + * 0 = port 0 DEVSLP on DEVSLP0/GPIO33 + * 1 = port 3 DEVSLP on DEVSLP0/GPIO33 + */ + uint8_t sata_devslp_mux; + + /* + * DEVSLP Disable + * 0: DEVSLP is enabled + * 1: DEVSLP is disabled + */ + uint8_t sata_devslp_disable; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* Enable linear PCIe Root Port function numbers starting at zero */ + uint8_t pcie_port_coalesce; + + /* Force root port ASPM configuration with port bitmap */ + uint8_t pcie_port_force_aspm; + + /* Put SerialIO devices into ACPI mode instead of a PCI device */ + uint8_t sio_acpi_mode; + + /* I2C voltage select: 0=3.3V 1=1.8V */ + uint8_t sio_i2c0_voltage; + uint8_t sio_i2c1_voltage; + + /* Enable ADSP power gating features */ + uint8_t adsp_d3_pg_enable; + uint8_t adsp_sram_pg_enable; + + /* + * Clock Disable Map: + * [21:16] = CLKOUT_PCIE# 5-0 + * [24] = CLKOUT_ITPXDP + */ + uint32_t icc_clock_disable; + + /* Deep SX enable */ + int deep_sx_enable_ac; + int deep_sx_enable_dc; +}; + +#endif diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 0d41d42..c98201e 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -13,7 +13,7 @@ #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/rcba.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h> #include <soc/cpu.h> #include <delay.h>
@@ -121,7 +121,7 @@ root_port_config_update_gbe_port();
pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); rpc.coalesce = config->pcie_port_coalesce; }
@@ -436,7 +436,7 @@
static void pch_pcie_early(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); int do_aspm = 0; int rp = root_port_number(dev);
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index d68e17e..149dda1 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -12,7 +12,7 @@ #include <soc/rcba.h> #include <soc/romstage.h> #include <soc/smbus.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h>
static void pch_route_interrupts(void) { @@ -52,9 +52,9 @@ static void pch_enable_lpc(void) { /* Lookup device tree in romstage */ - const config_t *config; + const struct device *const dev = pcidev_on_root(0x1f, 0);
- config = config_of_soc(); + const struct soc_intel_broadwell_pch_config *config = config_of(dev);
pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec); pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec); diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index c9168325..b496e53 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -11,7 +11,7 @@ #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/sata.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h>
static inline u32 sir_read(struct device *dev, int idx) { @@ -27,7 +27,7 @@
static void sata_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); u32 reg32; u8 *abar; u16 reg16; @@ -256,7 +256,7 @@ static void sata_enable(struct device *dev) { /* Get the chip configuration */ - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); u16 map = 0x0060;
map |= (config->sata_port_map ^ 0xf) << 8; diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 766f5dd..d32a27d 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -14,7 +14,7 @@ #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/serialio.h> -#include <soc/intel/broadwell/chip.h> +#include <soc/intel/broadwell/pch/chip.h>
/* Set D3Hot Power State in ACPI mode */ static void serialio_enable_d3hot(struct resource *res) @@ -156,7 +156,7 @@
static void serialio_init(struct device *dev) { - config_t *config = config_of(dev); + const struct soc_intel_broadwell_pch_config *config = config_of(dev); struct resource *bar0, *bar1; int sio_index = -1;
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index dc6f546..b9aeb38 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -472,12 +472,6 @@ dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; - } else if (dev->path.type == DEVICE_PATH_PCI) { - /* Handle PCH device enable */ - if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD && - (dev->ops == NULL || dev->ops->enable == NULL)) { - broadwell_pch_enable_dev(dev); - } } }
-
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Arthur Heymans (Code Review)