Change in coreboot[master]: [WIP]aopen/dxplplusu: Switch to PARALLEL_MP with SMM_ASEG - coreboot-gerrit

6 Apr 2022


      Attention is currently required from: Kyösti Mälkki, Patrick Rudolph.
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61517 )
Change subject: [WIP]aopen/dxplplusu: Switch to PARALLEL_MP with SMM_ASEG
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Patch Set 1:
(1 comment)
Patchset:
PS1: 
Sidenote: postcar_frame_add_mtrr(pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); in memmap.c can likely be dropped because final MTRRs are programmed on the BSP before the AP init?
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Gerrit-Project: coreboot
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Gerrit-Change-Id: If20a7092117612a1a9e25eb6ac480e105acd57d7
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