Change in coreboot[master]: soc/intel/cannonlake: Remove DMA support for PTT

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27176 )

Change subject: soc/intel/cannonlake: Remove DMA support for PTT
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Patch Set 3:
> Patch Set 3:
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> I am running into an issue on Whiskey Lake-U where the calculated reserved memory in coreboot is different from the calculated reserved memory in the FSP by 0x1000. Reverting this change fixes this miscalculation. Is it possible that this needs to be reinstated on some systems?

we do have WHL-U based several designs and don't see such issue, are you sure you are seeing issue because of this CL. its been a year old now ?

adding @bora owning WHL-U based design and @Lean Sheng for CFL based design