Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/27628
Change subject: mainboard/intel/coffeelake_rvp: Add new board ......................................................................
mainboard/intel/coffeelake_rvp: Add new board
Add new mainboard variant of whiskey lake rvp.
BUG=N/A TEST=Build and flash, confirm boot up into kernel on whiskeylake rvp platform.
Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Signed-off-by: Lijian Zhao lijian.zhao@intel.com --- M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/Kconfig.name M src/mainboard/intel/coffeelake_rvp/romstage.c M src/mainboard/intel/coffeelake_rvp/spd/spd_util.c A src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb A src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h 6 files changed, 191 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/27628/1
diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig b/src/mainboard/intel/coffeelake_rvp/Kconfig index 5bd7531..0af1723 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU +if BOARD_INTEL_COFFEELAKE_RVP11 || BOARD_INTEL_COFFEELAKE_RVPU || BOARD_INTEL_WHISKEYLAKE_RVP
config BOARD_SPECIFIC_OPTIONS def_bool y @@ -23,11 +23,13 @@ string default "cfl_u" if BOARD_INTEL_COFFEELAKE_RVPU default "cfl_h" if BOARD_INTEL_COFFEELAKE_RVP11 + default "whl_w" if BOARD_INTEL_WHISKEYLAKE_RVP
config MAINBOARD_PART_NUMBER string default "Coffeelake U RVP" if BOARD_INTEL_COFFEELAKE_RVPU default "Coffeelake H RVP11" if BOARD_INTEL_COFFEELAKE_RVP11 + default "Whiskeylake RVP" if BOARD_INTEL_WHISKEYLAKE_RVP
config MAINBOARD_VENDOR string diff --git a/src/mainboard/intel/coffeelake_rvp/Kconfig.name b/src/mainboard/intel/coffeelake_rvp/Kconfig.name index 0dc7079..9bf3ac8 100644 --- a/src/mainboard/intel/coffeelake_rvp/Kconfig.name +++ b/src/mainboard/intel/coffeelake_rvp/Kconfig.name @@ -2,3 +2,5 @@ bool "Coffeelake U LPDDR4 RVP" config BOARD_INTEL_COFFEELAKE_RVP11 bool "Coffeelake H LPDDR4 RVP11" +config BOARD_INTEL_WHISKEYLAKE_RVP + bool "Whiskeylake DDR4 RVP" diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c index e0699da..9fddc8b 100644 --- a/src/mainboard/intel/coffeelake_rvp/romstage.c +++ b/src/mainboard/intel/coffeelake_rvp/romstage.c @@ -27,7 +27,6 @@ { FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; - u8 spd_index;
mainboard_fill_dq_map_ch0(&mem_cfg->DqByteMapCh0); mainboard_fill_dq_map_ch1(&mem_cfg->DqByteMapCh1); @@ -36,10 +35,17 @@ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
- mem_cfg->DqPinsInterleaved = 0; - mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */ - mem_cfg->ECT = 1; /* Early Command Training Enabled */ - spd_index = 2; +#if !IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU) + mem_cfg->DqPinsInterleaved = 1; + mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA/CHB */ + + /* TODO: Hard coding SpdAddress */ + mem_cfg->SpdAddressTable[0] = 0xA0; + mem_cfg->SpdAddressTable[1] = 0xA2; + mem_cfg->SpdAddressTable[2] = 0xA4; + mem_cfg->SpdAddressTable[3] = 0xA6; +#else + u8 spd_index = 2;
struct region_device spd_rdev;
@@ -49,6 +55,7 @@ mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); /* Memory leak is ok since we have memory mapped boot media */ mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); - mem_cfg->RefClk = 0; /* Auto Select CLK freq */ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; +#endif + mem_cfg->SafeMode = 0; } diff --git a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c index c6f9511..48575ab 100644 --- a/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/coffeelake_rvp/spd/spd_util.c @@ -31,11 +31,18 @@
void mainboard_fill_dq_map_ch1(void *dq_map_ptr) { - const u8 dq_map[12] = { + const u8 dq_map_u[12] = { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
- memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); + const u8 dq_map_h[12] = { + 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU)) + memcpy(dq_map_ptr, dq_map_u, sizeof(dq_map_u)); + else + memcpy(dq_map_ptr, dq_map_h, sizeof(dq_map_h)); }
void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) @@ -43,12 +50,12 @@ /* DQS CPU<>DRAM map Ch0 */ const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 };
- const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 }; + const u8 dqs_map_h[8] = { 0, 1, 3, 2, 4, 5, 6, 7 };
if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU)) memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); + memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h)); }
void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) @@ -56,12 +63,12 @@ /* DQS CPU<>DRAM map Ch1 */ const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 };
- const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 }; + const u8 dqs_map_h[8] = { 1, 0, 4, 5, 3, 2, 6, 7 };
if (IS_ENABLED(CONFIG_BOARD_INTEL_COFFEELAKE_RVPU)) memcpy(dqs_map_ptr, dqs_map_u, sizeof(dqs_map_u)); else - memcpy(dqs_map_ptr, dqs_map_y, sizeof(dqs_map_y)); + memcpy(dqs_map_ptr, dqs_map_h, sizeof(dqs_map_h)); }
void mainboard_fill_rcomp_res_data(void *rcomp_ptr) diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb new file mode 100644 index 0000000..62a6635 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/devicetree.cb @@ -0,0 +1,139 @@ +chip soc/intel/cannonlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # FSP configuration + register "SaGv" = "3" + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" + register "ScsSdCardEnabled" = "1" + register "HeciEnabled" = "1" + + register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[8]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[9]" = "USB2_PORT_MID(OC0)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" + + register "SataEnable" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "1" + register "SataPortsEnable[7]" = "1" + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + + register "PcieRpEnable[0]" = "1" + register "PcieRpEnable[1]" = "1" + register "PcieRpEnable[2]" = "1" + register "PcieRpEnable[3]" = "1" + register "PcieRpEnable[4]" = "1" + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[6]" = "1" + register "PcieRpEnable[7]" = "1" + register "PcieRpEnable[8]" = "1" + register "PcieRpEnable[9]" = "1" + register "PcieRpEnable[10]" = "1" + register "PcieRpEnable[11]" = "1" + register "PcieRpEnable[12]" = "1" + register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1" + + register "PcieClkSrcUsage[0]" = "1" + register "PcieClkSrcUsage[1]" = "8" + register "PcieClkSrcUsage[2]" = "PCIE_CLK_LAN" + register "PcieClkSrcUsage[3]" = "13" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcUsage[5]" = "14" + + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPP_G5" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.3 on end # CNVi wifi + device pci 14.5 on end # SDCard + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 on end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 on end # UART #2 + device pci 1a.0 on end # eMMC + device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 + device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 off end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 on end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h new file mode 100644 index 0000000..4b6f579 --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/variants/whl_w/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include <baseboard/gpio.h> + +#endif /* __MAINBOARD_GPIO_H__ */
-
Lijian Zhao (Code Review)