Change in coreboot[master]: lib/fit_payload: Add coreboot tables support for FDT.

[Philipp Deppenwiese (Code Review)]

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/28104

Change subject: lib/fit_payload: Add coreboot tables support for FDT.
......................................................................

lib/fit_payload: Add coreboot tables support for FDT.

* Copy code of depthcharge boot/coreboot.c
  and modify it.

Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977
Signed-off-by: Philipp Deppenwiese 
---
M src/lib/fit_payload.c
1 file changed, 58 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/28104/1

diff --git a/src/lib/fit_payload.c b/src/lib/fit_payload.c
index 9dbd878..430a597 100644
--- a/src/lib/fit_payload.c
+++ b/src/lib/fit_payload.c
@@ -29,6 +29,8 @@
 #include <commonlib/compression.h>
 #include <lib.h>
 #include <fit_payload.h>
+#include <boardid.h>
+#include <arch/cbconfig.h>

/* Pack the device_tree and place it at given position. */
 static void pack_fdt(struct region *fdt, struct device_tree *dt)
@@ -96,6 +98,60 @@
    return false;
 }

+static void coreboot_fdt_data(struct device_tree *tree)
+{
+	u32 addr_cells = 1, size_cells = 1;
+	static const char *firmware_path[] const = {"firmware", NULL};
+	struct device_tree_node *firmware_node = dt_find_node(tree->root,
+		firmware_path, &addr_cells, &size_cells, 1);
+
+	// Need to add 'ranges' to the intermediate node to make 'reg' work.
+	dt_add_bin_prop(firmware_node, "ranges", NULL, 0);
+
+	static const char *coreboot_path[] const = {"coreboot", NULL};
+	struct device_tree_node *coreboot_node = dt_find_node(firmware_node,
+		coreboot_path, &addr_cells, &size_cells, 1);
+
+	dt_add_string_prop(coreboot_node, "compatible", (char *)"coreboot");
+
+	// Fetch CB tables from cbmem
+	void *cbtable = cbmem_find(CBMEM_ID_CBTABLE);
+	if (!cbtable) {
+		printk(BIOS_WARNING, "FIT: No coreboot table found!\n");
+		return;
+	}
+
+	u64 reg_addrs[2];
+	u64 reg_sizes[2];
+
+	// First 'reg' address range is the coreboot table.
+	struct lb_header *header = cbtable;
+	reg_addrs[0] = (uintptr_t)header;
+	reg_sizes[0] = header->header_bytes + header->table_bytes;
+
+	// Second is the CBMEM area (which usually includes the coreboot table).
+	reg_addrs[1] = (uintptr_t)cbmem_top();
+	reg_sizes[1] = cbmem_overhead_size();
+
+	dt_add_reg_prop(coreboot_node, reg_addrs, reg_sizes, 2,
+			addr_cells, size_cells);
+
+	// Expose board ID, SKU ID, and RAM code exported from coreboot to
+	// userspace.
+	if (board_id() != UNDEFINED_STRAPPING_ID) {
+		dt_add_u32_prop(coreboot_node,
+				"board-id", board_id());
+	}
+	if (sku_id() != UNDEFINED_STRAPPING_ID) {
+		dt_add_u32_prop(coreboot_node,
+				"sku-id", sku_id());
+	}
+	if (ram_code() != UNDEFINED_STRAPPING_ID) {
+		dt_add_u32_prop(coreboot_node,
+				"ram-code", ram_code());
+	}
+}
+
 /*
  * Parse the uImage FIT, choose a configuration and extract images.
  */
@@ -129,6 +185,8 @@
    		return;
    	}

+		// Insert coreboot specific information
+		coreboot_fdt_data(dt);
    	dt_apply_fixups(dt);

/* Update device_tree */