Change in coreboot[master]: [WIP]amdfwtool: Use relative address for EFS gen2

[Bao Zheng (Code Review)]

Attention is currently required from: Zheng Bao.
Hello Zheng Bao,

I'd like you to do a code review. Please visit

https://review.coreboot.org/c/coreboot/+/56438

to review the following change.

Change subject: [WIP]amdfwtool: Use relative address for EFS gen2
......................................................................

[WIP]amdfwtool: Use relative address for EFS gen2

The second generation EFS (offset 0x24[0]=0) uses
"binary relative" offsets and not "x86 physical
MMIO address" like gen1.

Chips like Cezanne can run in both cases, so no problem
comes up so far.

TODO: Need to fix the problem in psp_verstage.

BUG=b:188754219
Test=Majolica (Cezanne)

Change-Id: I7701c7819f03586d4ecab3d744056c8c902b630f
Signed-off-by: Zheng Bao 
---
M util/amdfwtool/amdfwtool.c
1 file changed, 9 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/56438/1

diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 4ec9edf..b4d1c0c 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -343,11 +343,12 @@
 typedef struct _context {
    char *rom;		/* target buffer, size of flash device */
    uint32_t rom_size;	/* size of flash device */
+	uint32_t abs_address;	/* produce absolute or relative address */
    uint32_t current;	/* pointer within flash & proxy buffer */
 } context;

#define RUN_BASE(ctx) (0xFFFFFFFF - (ctx).rom_size + 1)
-#define RUN_OFFSET(ctx, offset) (RUN_BASE(ctx) + (offset))
+#define RUN_OFFSET(ctx, offset) ((ctx).abs_address ? RUN_BASE(ctx) + (offset) : (offset))
 #define RUN_CURRENT(ctx) RUN_OFFSET((ctx), (ctx).current)
 #define BUFF_OFFSET(ctx, offset) ((void *)((ctx).rom + (offset)))
 #define BUFF_CURRENT(ctx) BUFF_OFFSET((ctx), (ctx).current)
@@ -1536,8 +1537,6 @@
    	romsig_offset = ctx.current = dir_location - rom_base_address;
    else
    	romsig_offset = ctx.current = AMD_ROMSIG_OFFSET;
-	printf("    AMDFWTOOL  Using firmware directory location of 0x%08x\n",
-			RUN_CURRENT(ctx));

amd_romsig = BUFF_OFFSET(ctx, romsig_offset);
    amd_romsig->signature = EMBEDDED_FW_SIGNATURE;
@@ -1556,6 +1555,13 @@
    	fprintf(stderr, "WARNING: No SOC name specified.\n");
    }

+	if (amd_romsig->efs_gen.gen == EFS_SECOND_GEN)
+		ctx.abs_address = 0;
+	else
+		ctx.abs_address = 1;
+	printf("    AMDFWTOOL  Using firmware directory location of %s address: 0x%08x\n",
+			ctx.abs_address == 1 ? "absolute" : "relative", RUN_CURRENT(ctx));
+
    integrate_firmwares(&ctx, amd_romsig, amd_fw_table);

ctx.current = ALIGN(ctx.current, 0x10000U); /* TODO: is it necessary? */