Change in coreboot[master]: soc/amd/stoneyridge: Fix 80+ characters lines

[Richard Spiegel (Code Review)]

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29228

Change subject: soc/amd/stoneyridge: Fix 80+ characters lines
......................................................................

soc/amd/stoneyridge: Fix 80+ characters lines

There some files that do have at least 1 line over the 80 characters limit.
Find and fix them.

BUG=b:117950052
TEST=Build grunt.

Change-Id: I1083a7559919e05a3e3a2dac99f571c161bb4c27
Signed-off-by: Richard Spiegel 
---
M src/soc/amd/common/block/pci/amd_pci_util.c
M src/soc/amd/stoneyridge/include/soc/nvs.h
M src/soc/amd/stoneyridge/northbridge.c
3 files changed, 9 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/29228/1

diff --git a/src/soc/amd/common/block/pci/amd_pci_util.c b/src/soc/amd/common/block/pci/amd_pci_util.c
index 8127601..e0b3c3d 100644
--- a/src/soc/amd/common/block/pci/amd_pci_util.c
+++ b/src/soc/amd/common/block/pci/amd_pci_util.c
@@ -98,7 +98,9 @@
 void write_pci_cfg_irqs(void)
 {
    struct device *dev = NULL;  /* Our current device to route IRQs */
-	struct device *target_dev = NULL; /* to bridge a device may be connected to */
+	struct device *target_dev = NULL; /* the bridge a device may be
+					   *connected to
+					   */
    u16 int_pin = 0;      /* Value of the INT_PIN register 0x3D */
    u16 target_pin = 0;   /* Pin we will search our tables for */
    u16 int_line = 0;     /* IRQ # read from PCI_INTR tbl and write to 3C */
diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h
index 3e6ef30..7578f9d 100644
--- a/src/soc/amd/stoneyridge/include/soc/nvs.h
+++ b/src/soc/amd/stoneyridge/include/soc/nvs.h
@@ -43,7 +43,9 @@
    uint32_t	nhll; /* 0x21 - 0x24 - NHLT Length */
    uint32_t	prt0; /* 0x25 - 0x28 - PERST_0 Address */
    uint8_t		scdp; /* 0x29 - SD_CD GPIO portid */
-	uint8_t		scdo; /* 0x2A - GPIO pad offset relative to the community */
+	uint8_t		scdo; /* 0x2A - GPIO pad offset relative
+			       *	to the community
+			       */
    uint8_t		tmps; /* 0x2B - Temperature Sensor ID */
    uint8_t		tlvl; /* 0x2C - Throttle Level Limit */
    uint8_t		flvl; /* 0x2D - Current FAN Level */
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index d17d855..88a74b0 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -86,7 +86,9 @@
    res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }

-static void set_resource(struct device *dev, struct resource *resource, u32 nodeid)
+static void set_resource(struct device *dev,
+			 struct resource *resource,
+			 u32 nodeid)
 {
    resource_t rbase, rend;
    unsigned int reg, link_num;