[M] Change in coreboot[master]: [TESTME] mb/google/kahlee/mainboard: rewrite IRQ mapping handling
Attention is currently required from: Jason Nien, Martin Roth.
Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/68851 )
Change subject: [TESTME] mb/google/kahlee/mainboard: rewrite IRQ mapping handling ......................................................................
[TESTME] mb/google/kahlee/mainboard: rewrite IRQ mapping handling
Rewrite the Kahlee IRQ mapping handling to be in line with the newer AMD SoCs to allow making the largest part of the corresponding code common for all AMD SoCs in the coreboot tree.
The PIC-mode IRQ numbers for both PIRQ_ASF and PIRQ_SDIO were 0 in the data tables which is the PIT IRQ which looks very wrong to me, so it was changed to PIRQ_NC. Since the ASF and likely also the SDIO controller are unused, this shouldn't change runtime behavior. The data tables also had non 0 and non 0x1f entries in the following locations the internal BKDG describes as unused: 0x31-0x33, 0x35-0x37, 0x40, 0x50-0x53
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I9b3bfca33d88ef3989b63f4fe6c301e0e485b7e9 --- M src/mainboard/google/kahlee/mainboard.c 1 file changed, 85 insertions(+), 41 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/68851/1
diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 196d6b8..3433f8b 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -18,55 +18,77 @@ #include <variant/ec.h> #include <variant/thermal.h>
-/*********************************************************** +/* * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. * This table is responsible for physically routing the PIC and * IOAPIC IRQs to the different PCI devices on the system. It * is read and written via registers 0xC00/0xC01 as an * Index/Data pair. These values are chipset and mainboard * dependent and should be updated accordingly. - * - * These values are used by the PCI configuration space, - * MP Tables. TODO: Make ACPI use these values too. */ +static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; +static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES];
-static const u8 mainboard_picr_data[FCH_IRQ_ROUTING_ENTRIES] = { - [0x00] = 0x03, 0x04, 0x05, 0x07, 0x0B, 0x1F, 0x1F, 0x1F, - [0x08] = 0xFA, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x09, 0x1F, 0x1F, 0x03, 0x1F, 0x1F, 0x1F, 0x03, - [0x18] = 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x05, 0x04, 0x05, 0x04, 0x04, 0x05, 0x04, 0x05, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x04, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x03, 0x04, 0x05, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, - [0x58] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x60] = 0x1F, 0x1F, 0x07, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x68] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, +static const struct fch_irq_routing fch_irq_map[] = { + { PIRQ_A, 3, 16 }, + { PIRQ_B, 4, 17 }, + { PIRQ_C, 5, 18 }, + { PIRQ_D, 7, 19 }, + { PIRQ_E, 11, 20 }, + { PIRQ_F, PIRQ_NC, PIRQ_NC }, + { PIRQ_G, PIRQ_NC, 22 }, + { PIRQ_H, PIRQ_NC, 23 }, + { PIRQ_SCI, 9, 9 }, + { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC }, + { PIRQ_HDA, 3, 16 }, + { PIRQ_SD, 3, 16 }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_EHCI, 5, 18 }, + { PIRQ_XHCI, 4, 18 }, + { PIRQ_SATA, 4, 19 }, + { PIRQ_GPIO, 7, 7 }, + { PIRQ_I2C0, 3, 3 }, + { PIRQ_I2C1, 15, 15 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 14, 14 }, + { PIRQ_UART0, 10, 10 }, + { PIRQ_UART1, 11, 11 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0xf1, 0x00 }, + { PIRQ_MISC1, 0x00, 0x00 }, + { PIRQ_MISC2, 0x00, 0x00 }, };
-static const u8 mainboard_intr_data[FCH_IRQ_ROUTING_ENTRIES] = { - [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x1F, 0x16, 0x17, - [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, - [0x10] = 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x1F, 0x1F, 0x10, - [0x18] = 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x20] = 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, - [0x28] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x30] = 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, - [0x38] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x40] = 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x48] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x50] = 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, - [0x58] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x60] = 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x68] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - [0x70] = 0x03, 0x0F, 0x06, 0x0E, 0x0A, 0x0B, 0x1F, 0x1F, - [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -}; +static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) +{ + *length = ARRAY_SIZE(fch_irq_map); + return fch_irq_map; +} + +static void init_tables(void) +{ + const struct fch_irq_routing *mb_irq_map; + size_t mb_fch_irq_mapping_table_size; + size_t i; + + mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); + + memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); + memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); + + for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { + if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { + printk(BIOS_WARNING, + "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", + mb_irq_map[i].intr_index, i); + continue; + } + fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; + fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; + } +}
/* * This table defines the index into the picr/intr_data tables for each @@ -95,8 +117,8 @@ { pirq_data_ptr = mainboard_pirq_data; pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); - intr_data_ptr = mainboard_intr_data; - picr_data_ptr = mainboard_picr_data; + intr_data_ptr = fch_apic_routing; + picr_data_ptr = fch_pic_routing; }
void __weak variant_devtree_update(void) @@ -143,6 +165,7 @@ *************************************************/ static void mainboard_enable(struct device *dev) { + init_tables(); /* Initialize the PIRQ data structures for consumption */ pirq_setup();
-
Felix Held (Code Review)