Hello ashk@codeaurora.org,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/35502
to review the following change.
Change subject: sc7180: Add AOP firmware support ......................................................................
sc7180: Add AOP firmware support
Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25210/85
Change-Id: I1cd552fbf03b5135e5911f1143f8778cad81e360 Signed-off-by: ashk ashk@codeaurora.org --- M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/aop_load_reset.c A src/soc/qualcomm/sc7180/include/soc/aop.h M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/mmu.c M src/soc/qualcomm/sc7180/soc.c 7 files changed, 89 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35502/1
diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index 7ad0328..d8fc33a 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -48,6 +48,7 @@ ramstage-y += qcom_qup_se.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c +ramstage-y += aop_load_reset.c
################################################################################
diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c new file mode 100644 index 0000000..8d22d62 --- /dev/null +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/cache.h> +#include <cbfs.h> +#include <halt.h> +#include <console/console.h> +#include <timestamp.h> +#include <soc/mmu.h> +#include <soc/aop.h> +#include <soc/clock.h> + +void aop_fw_load_reset(void) +{ + bool aop_fw_entry; + + struct prog aop_fw_prog = + PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); + + if (prog_locate(&aop_fw_prog)) + die("SOC image: AOP_FW not found"); + + aop_fw_entry = selfload(&aop_fw_prog); + if (!aop_fw_entry) + die("SOC image: AOP load failed"); + + clock_reset_aop(); + + printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); +} diff --git a/src/soc/qualcomm/sc7180/include/soc/aop.h b/src/soc/qualcomm/sc7180/include/soc/aop.h new file mode 100644 index 0000000..5573163 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/aop.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_AOP_H__ +#define _SOC_QUALCOMM_SC7180_AOP_H__ + +void aop_fw_load_reset(void); + +#endif // _SOC_QUALCOMM_SC7180_AOP_H__ diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index ae00816..f4e6f05 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -24,8 +24,24 @@ #define BSRAM_START(addr) SYMBOL(bsram, addr) #define BSRAM_END(addr) SYMBOL(ebsram, addr)
+/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) +#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) + +/* AOPMSG : 0x0C300000 - 0x0C400000 */ +#define AOPMSG_START(addr) SYMBOL(aopmsg, addr) +#define AOPMSG_END(addr) SYMBOL(eaopmsg, addr) + SECTIONS { + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + + AOPMSG_START(0x0C300000) + REGION(aop_ss_msg_ram_drv15, 0x0C3F0000, 0x400, 0x100) + AOPMSG_END(0x0C400000) + SSRAM_START(0x14680000) OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) REGION(qcsdi, 0x14699000, 52K, 4K) diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index 14b779f..893ecc3 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -26,5 +26,7 @@ DECLARE_REGION(dcb); DECLARE_REGION(pmic); DECLARE_REGION(limits_cfg); +DECLARE_REGION(aop); +DECLARE_REGION(aop_ss_msg_ram_drv15);
#endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index fd59a5a..2eb8c86 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -33,3 +33,7 @@ mmu_enable(); }
+void soc_mmu_dram_config_post_dram_init(void) +{ + mmu_config_range((void *)_aop, REGION_SIZE(aop), CACHED_RAM); +} diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 4fc5b30..7039935 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -18,6 +18,7 @@ #include <soc/mmu.h> #include <soc/mmu_common.h> #include <soc/symbols.h> +#include <soc/aop.h>
static void soc_read_resources(struct device *dev) { @@ -34,7 +35,7 @@
static void soc_init(struct device *dev) { - + aop_fw_load_reset(); }
static struct device_operations soc_ops = {
Hello Julius Werner, ashk@codeaurora.org, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35502
to look at the new patch set (#3).
Change subject: sc7180: Add AOP firmware support ......................................................................
sc7180: Add AOP firmware support
Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25210/85
Change-Id: I1cd552fbf03b5135e5911f1143f8778cad81e360 Signed-off-by: ashk ashk@codeaurora.org --- M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/aop_load_reset.c A src/soc/qualcomm/sc7180/include/soc/aop.h M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/mmu.c M src/soc/qualcomm/sc7180/soc.c 7 files changed, 90 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35502/3
Hello Julius Werner, ashk@codeaurora.org, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35502
to look at the new patch set (#7).
Change subject: sc7180: Add AOP firmware support ......................................................................
sc7180: Add AOP firmware support
Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25210/85
Change-Id: I1cd552fbf03b5135e5911f1143f8778cad81e360 Signed-off-by: Ashwin Kumar ashk@codeaurora.org --- M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/aop_load_reset.c A src/soc/qualcomm/sc7180/include/soc/aop.h M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/mmu.c M src/soc/qualcomm/sc7180/soc.c 7 files changed, 95 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35502/7
Hello Julius Werner, ashk@codeaurora.org, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35502
to look at the new patch set (#8).
Change subject: sc7180: Add AOP firmware support ......................................................................
sc7180: Add AOP firmware support
Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25210/85
Change-Id: I1cd552fbf03b5135e5911f1143f8778cad81e360 Signed-off-by: Ashwin Kumar ashk@codeaurora.org --- M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/aop_load_reset.c A src/soc/qualcomm/sc7180/include/soc/aop.h M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/mmu.c M src/soc/qualcomm/sc7180/soc.c 7 files changed, 94 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35502/8
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35502 )
Change subject: sc7180: Add AOP firmware support ......................................................................
Patch Set 11: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/35502/11/src/soc/qualcomm/sc7180/in... File src/soc/qualcomm/sc7180/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/35502/11/src/soc/qualcomm/sc7180/in... PS11, Line 70: REGION(dram_aop, 0x80800000, 0x040000, 0x1000) SDM845 didn't have this, what is this? Can we make it contiguous with the other reserved area?
Ravi kumar has uploaded a new patch set (#14) to the change originally created by mturney mturney. ( https://review.coreboot.org/c/coreboot/+/35502 )
Change subject: sc7180: Add AOP firmware support ......................................................................
sc7180: Add AOP firmware support
Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25210/85
Change-Id: I1cd552fbf03b5135e5911f1143f8778cad81e360 Signed-off-by: Ashwin Kumar ashk@codeaurora.org --- M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/aop_load_reset.c A src/soc/qualcomm/sc7180/include/soc/aop.h M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/mmu.c M src/soc/qualcomm/sc7180/soc.c 7 files changed, 85 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/35502/14
mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35502 )
Change subject: sc7180: Add AOP firmware support ......................................................................
Patch Set 14:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35502/11/src/soc/qualcomm/sc7180/in... File src/soc/qualcomm/sc7180/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/35502/11/src/soc/qualcomm/sc7180/in... PS11, Line 70: REGION(dram_aop, 0x80800000, 0x040000, 0x1000)
SDM845 didn't have this, what is this? Can we make it contiguous with the other reserved area?
I can't speak to why this is different between Rennell and Napali other than cite hardware deltas. However the Rennell memory map lists an AOP region both in SRAM and DRAM that must be reserved. The areas we have set aside in memlayout.ld are consistent with the internal memory layout of the chip.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35502 )
Change subject: sc7180: Add AOP firmware support ......................................................................
Patch Set 14: Code-Review+2
(1 comment)
https://review.coreboot.org/c/coreboot/+/35502/11/src/soc/qualcomm/sc7180/in... File src/soc/qualcomm/sc7180/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/35502/11/src/soc/qualcomm/sc7180/in... PS11, Line 70: REGION(dram_aop, 0x80800000, 0x040000, 0x1000)
I can't speak to why this is different between Rennell and Napali other than cite hardware deltas. […]
Hmm... looks like I don't have that document, the memory map we were given only goes up to 0x10000000. But okay, if this is a standardized location on this SoC there's nothing wrong with that, I'm just curious where it suddenly came from (because the two chips are so similar otherwise).
With the code we have in depthcharge right now the remaining 756KB hole here will not be passed through to the kernel anyway, because we align everything by 1MB. Maybe we should change that (it's not really necessary anymore).
mturney mturney has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35502 )
Change subject: sc7180: Add AOP firmware support ......................................................................
Patch Set 15:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35502/11/src/soc/qualcomm/sc7180/in... File src/soc/qualcomm/sc7180/include/soc/memlayout.ld:
https://review.coreboot.org/c/coreboot/+/35502/11/src/soc/qualcomm/sc7180/in... PS11, Line 70: REGION(dram_aop, 0x80800000, 0x040000, 0x1000)
Hmm... […]
Julius, Do you want to leave as-is or change to: REGION(dram_aop, 0x80800000, 0x100000, 0x1000)
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35502 )
Change subject: sc7180: Add AOP firmware support ......................................................................
sc7180: Add AOP firmware support
Developer/Reviewer, be aware of this patch from Napali: https://review.coreboot.org/c/coreboot/+/25210/85
Change-Id: I1cd552fbf03b5135e5911f1143f8778cad81e360 Signed-off-by: Ashwin Kumar ashk@codeaurora.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/35502 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Julius Werner jwerner@chromium.org --- M src/soc/qualcomm/sc7180/Makefile.inc A src/soc/qualcomm/sc7180/aop_load_reset.c A src/soc/qualcomm/sc7180/include/soc/aop.h M src/soc/qualcomm/sc7180/include/soc/memlayout.ld M src/soc/qualcomm/sc7180/include/soc/symbols.h M src/soc/qualcomm/sc7180/mmu.c M src/soc/qualcomm/sc7180/soc.c 7 files changed, 85 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved
diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc index e1d0492..8a76a03 100644 --- a/src/soc/qualcomm/sc7180/Makefile.inc +++ b/src/soc/qualcomm/sc7180/Makefile.inc @@ -40,6 +40,7 @@ ramstage-$(CONFIG_DRIVERS_UART) += uart_bitbang.c ramstage-y += clock.c ramstage-$(CONFIG_SC7180_QSPI) += qspi.c +ramstage-y += aop_load_reset.c
################################################################################
diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c new file mode 100644 index 0000000..8d22d62 --- /dev/null +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/cache.h> +#include <cbfs.h> +#include <halt.h> +#include <console/console.h> +#include <timestamp.h> +#include <soc/mmu.h> +#include <soc/aop.h> +#include <soc/clock.h> + +void aop_fw_load_reset(void) +{ + bool aop_fw_entry; + + struct prog aop_fw_prog = + PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/aop"); + + if (prog_locate(&aop_fw_prog)) + die("SOC image: AOP_FW not found"); + + aop_fw_entry = selfload(&aop_fw_prog); + if (!aop_fw_entry) + die("SOC image: AOP load failed"); + + clock_reset_aop(); + + printk(BIOS_DEBUG, "\nSOC:AOP brought out of reset.\n"); +} diff --git a/src/soc/qualcomm/sc7180/include/soc/aop.h b/src/soc/qualcomm/sc7180/include/soc/aop.h new file mode 100644 index 0000000..5573163 --- /dev/null +++ b/src/soc/qualcomm/sc7180/include/soc/aop.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_QUALCOMM_SC7180_AOP_H__ +#define _SOC_QUALCOMM_SC7180_AOP_H__ + +void aop_fw_load_reset(void); + +#endif // _SOC_QUALCOMM_SC7180_AOP_H__ diff --git a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld index 3f43419..7323119 100644 --- a/src/soc/qualcomm/sc7180/include/soc/memlayout.ld +++ b/src/soc/qualcomm/sc7180/include/soc/memlayout.ld @@ -24,8 +24,16 @@ #define BSRAM_START(addr) SYMBOL(bsram, addr) #define BSRAM_END(addr) SYMBOL(ebsram, addr)
+/* AOP : 0x0B000000 - 0x0B100000 */ +#define AOPSRAM_START(addr) SYMBOL(aopsram, addr) +#define AOPSRAM_END(addr) SYMBOL(eaopsram, addr) + SECTIONS { + AOPSRAM_START(0x0B000000) + REGION(aop, 0x0B000000, 0x100000, 4096) + AOPSRAM_END(0x0B100000) + SSRAM_START(0x14680000) OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 100K) REGION(qcsdi, 0x14699000, 52K, 4K) @@ -52,6 +60,7 @@
DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ + REGION(dram_aop, 0x80800000, 0x040000, 0x1000) REGION(dram_soc, 0x80900000, 0x300000, 0x1000) BL31(0x80C00000, 0x1A800000) POSTRAM_CBFS_CACHE(0x9F800000, 16M) diff --git a/src/soc/qualcomm/sc7180/include/soc/symbols.h b/src/soc/qualcomm/sc7180/include/soc/symbols.h index f379bb9..d2a53fb 100644 --- a/src/soc/qualcomm/sc7180/include/soc/symbols.h +++ b/src/soc/qualcomm/sc7180/include/soc/symbols.h @@ -25,5 +25,6 @@ DECLARE_REGION(dcb) DECLARE_REGION(pmic) DECLARE_REGION(limits_cfg) +DECLARE_REGION(aop)
#endif /* _SOC_QUALCOMM_SC7180_SYMBOLS_H_ */ diff --git a/src/soc/qualcomm/sc7180/mmu.c b/src/soc/qualcomm/sc7180/mmu.c index 231b06f..2eb8c86 100644 --- a/src/soc/qualcomm/sc7180/mmu.c +++ b/src/soc/qualcomm/sc7180/mmu.c @@ -32,3 +32,8 @@
mmu_enable(); } + +void soc_mmu_dram_config_post_dram_init(void) +{ + mmu_config_range((void *)_aop, REGION_SIZE(aop), CACHED_RAM); +} diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 7003b39..fbcfc6e 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -18,18 +18,21 @@ #include <soc/mmu.h> #include <soc/mmu_common.h> #include <soc/symbols.h> +#include <soc/aop.h>
static void soc_read_resources(struct device *dev) { ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB, ddr_region->size / KiB); - reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB, + reserved_ram_resource(dev, 1, (uintptr_t)_dram_aop / KiB, + REGION_SIZE(dram_aop) / KiB); + reserved_ram_resource(dev, 2, (uintptr_t)_dram_soc / KiB, REGION_SIZE(dram_soc) / KiB); }
static void soc_init(struct device *dev) { - + aop_fw_load_reset(); }
static struct device_operations soc_ops = {
-
Julius Werner (Code Review) -
mturney mturney (Code Review)
-
Patrick Georgi (Code Review)
-
Ravi kumar (Code Review)