Change in coreboot[master]: mb/google/guybrush/bootblock: drop redundant clearing of LPC decodes

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/58341 )

Change subject: mb/google/guybrush/bootblock: drop redundant clearing of LPC decodes
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mb/google/guybrush/bootblock: drop redundant clearing of LPC decodes

The writes were originally added due to being part of the initialization
sequence in the reference code, but coreboot already has those registers
cleared by the time we reach this part of the code, so we can drop these
redundant writes.

Signed-off-by: Felix Held 
Change-Id: I43344460e5355664841d77daf1df3fd386e047e9
---
M src/mainboard/google/guybrush/bootblock.c
1 file changed, 5 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/58341/1

diff --git a/src/mainboard/google/guybrush/bootblock.c b/src/mainboard/google/guybrush/bootblock.c
index 040bc52..4a0d384 100644
--- a/src/mainboard/google/guybrush/bootblock.c
+++ b/src/mainboard/google/guybrush/bootblock.c
@@ -39,8 +39,11 @@
    dword |= LPC_LDRQ0_PD_EN;
    pci_write_config32(SOC_LPC_DEV, LPC_MISC_CONTROL_BITS, dword);

-	pci_write_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, 0);
-	pci_write_config32(SOC_LPC_DEV, LPC_IO_OR_MEM_DECODE_ENABLE, 0);
+	/*
+	 * All LPC decodes need to be cleared before we can configure the LPC pads as secondary
+	 * eSPI interface that gets used for the EC communication. This is already done by
+	 * lpc_disable_decodes that gets called before this function.
+	 */

if (CONFIG(VBOOT_STARTS_BEFORE_BOOTBLOCK))
    	return;