Lean Sheng Tan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48127 )
Change subject: mb/intel/ehlcrb: Add EHL CRB memory initialization support ......................................................................
mb/intel/ehlcrb: Add EHL CRB memory initialization support
Update memory parameters based on memory type supported by Elkhart Lake CRB:
1. Update spd data for EHL LPDDR4X memory - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Add configurations for vref_ca & interleaved memory 3. Add EHL CRB on board LPDDR4X SPD data bin file 4. Update mainboard related FSPM UPDs as part of memory initialization
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b --- M src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c M src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc A src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c M src/soc/intel/elkhartlake/include/soc/meminit.h M src/soc/intel/elkhartlake/meminit.c 6 files changed, 115 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/48127/1
diff --git a/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c index 481ff09..3240834 100644 --- a/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c +++ b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c @@ -7,5 +7,15 @@
void mainboard_memory_init_params(FSPM_UPD *memupd) { - /* ToDo : Fill FSP-M spd related memory params */ + static struct spd_info ehlcrb_spd_info; + const struct mb_cfg *board_cfg = variant_memcfg_config(); + + /* TODO: Read the resistor strap to get number of memory segments */ + bool half_populated = false; + /* Initialize spd information for LPDDR4x board */ + ehlcrb_spd_info.read_type = READ_SPD_CBFS; + ehlcrb_spd_info.spd_spec.spd_index = 0x00; + + /* Initialize variant specific configurations */ + memcfg_init(&memupd->FspmConfig, board_cfg, &ehlcrb_spd_info, half_populated); } diff --git a/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc index 1af6515..70494b5 100644 --- a/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc +++ b/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc @@ -1,3 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-only
-SPD_SOURCES = empty # 0b000 +SPD_SOURCES = ehlcrb # 0b000 diff --git a/src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex b/src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex new file mode 100644 index 0000000..71e5456 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c index 11db732..0f1dd69 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c @@ -5,4 +5,56 @@ #include <soc/meminit.h> #include <soc/romstage.h>
-/* ToDo : Fill EHL related memory configs */ +static const struct mb_cfg ehlcrb_lpddr4x_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6}, + .dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6}, + + /* Baseboard uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {60, 40, 30, 20, 30}, + + /* LPDDR4x does not allow interleaved memory */ + .dq_pins_interleaved = 0, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, + + /* Set Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memcfg_config(void) +{ + return &ehlcrb_lpddr4x_memcfg_cfg; +} diff --git a/src/soc/intel/elkhartlake/include/soc/meminit.h b/src/soc/intel/elkhartlake/include/soc/meminit.h index ea4664a..2dcbd13 100644 --- a/src/soc/intel/elkhartlake/include/soc/meminit.h +++ b/src/soc/intel/elkhartlake/include/soc/meminit.h @@ -88,11 +88,26 @@
/* * Rcomp target values. These will typically be the following - * values for Elkhart Lake : { 80, 40, 40, 40, 30 } + * values for Elkhart Lake : { 60, 40, 30, 20, 30 } */ uint16_t rcomp_targets[5];
/* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + uint8_t dq_pins_interleaved; + + /* + * VREF_CA configuration. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + uint8_t vref_ca_config; + + /* * Early Command Training Enable/Disable Control * 1 = enable, 0 = disable */ diff --git a/src/soc/intel/elkhartlake/meminit.c b/src/soc/intel/elkhartlake/meminit.c index cd777ba..f1f8270 100644 --- a/src/soc/intel/elkhartlake/meminit.c +++ b/src/soc/intel/elkhartlake/meminit.c @@ -109,6 +109,7 @@
/* Early Command Training Enabled */ mem_cfg->ECT = board_cfg->ect; - + mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; + mem_cfg->CaVrefConfig = board_cfg->vref_ca_config; mem_cfg->UserBd = board_cfg->UserBd; }
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48127 )
Change subject: mb/intel/ehlcrb: Add EHL CRB memory initialization support ......................................................................
Patch Set 1: Code-Review+1
(1 comment)
https://review.coreboot.org/c/coreboot/+/48127/1/src/mainboard/intel/elkhart... File src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c:
https://review.coreboot.org/c/coreboot/+/48127/1/src/mainboard/intel/elkhart... PS1, Line 41: /* Baseboard Rcomp target values */ This comment does not add more information than the code already do. You could drop it without loss of information.
Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Maulik V Vaghela, Mario Scheithauer, Subrata Banik, Werner Zeh, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48127
to look at the new patch set (#2).
Change subject: mb/intel/ehlcrb: Add EHL CRB memory initialization support ......................................................................
mb/intel/ehlcrb: Add EHL CRB memory initialization support
Update memory parameters based on memory type supported by Elkhart Lake CRB:
1. Update spd data for EHL LPDDR4X memory - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Add configurations for vref_ca & interleaved memory 3. Add EHL CRB on board LPDDR4X SPD data bin file 4. Update mainboard related FSPM UPDs as part of memory initialization
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b --- M src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c M src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc A src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c M src/soc/intel/elkhartlake/include/soc/meminit.h M src/soc/intel/elkhartlake/meminit.c 6 files changed, 114 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/48127/2
Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48127 )
Change subject: mb/intel/ehlcrb: Add EHL CRB memory initialization support ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48127/1/src/mainboard/intel/elkhart... File src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c:
https://review.coreboot.org/c/coreboot/+/48127/1/src/mainboard/intel/elkhart... PS1, Line 41: /* Baseboard Rcomp target values */
This comment does not add more information than the code already do. […]
Done
Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48127 )
Change subject: mb/intel/ehlcrb: Add EHL CRB memory initialization support ......................................................................
Patch Set 2: Code-Review+2
Werner Zeh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48127 )
Change subject: mb/intel/ehlcrb: Add EHL CRB memory initialization support ......................................................................
mb/intel/ehlcrb: Add EHL CRB memory initialization support
Update memory parameters based on memory type supported by Elkhart Lake CRB:
1. Update spd data for EHL LPDDR4X memory - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Add configurations for vref_ca & interleaved memory 3. Add EHL CRB on board LPDDR4X SPD data bin file 4. Update mainboard related FSPM UPDs as part of memory initialization
Signed-off-by: Tan, Lean Sheng lean.sheng.tan@intel.com Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Werner Zeh werner.zeh@siemens.com --- M src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c M src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc A src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c M src/soc/intel/elkhartlake/include/soc/meminit.h M src/soc/intel/elkhartlake/meminit.c 6 files changed, 114 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved
diff --git a/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c index 481ff09..3240834 100644 --- a/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c +++ b/src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c @@ -7,5 +7,15 @@
void mainboard_memory_init_params(FSPM_UPD *memupd) { - /* ToDo : Fill FSP-M spd related memory params */ + static struct spd_info ehlcrb_spd_info; + const struct mb_cfg *board_cfg = variant_memcfg_config(); + + /* TODO: Read the resistor strap to get number of memory segments */ + bool half_populated = false; + /* Initialize spd information for LPDDR4x board */ + ehlcrb_spd_info.read_type = READ_SPD_CBFS; + ehlcrb_spd_info.spd_spec.spd_index = 0x00; + + /* Initialize variant specific configurations */ + memcfg_init(&memupd->FspmConfig, board_cfg, &ehlcrb_spd_info, half_populated); } diff --git a/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc b/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc index 1af6515..70494b5 100644 --- a/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc +++ b/src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc @@ -1,3 +1,3 @@ ## SPDX-License-Identifier: GPL-2.0-only
-SPD_SOURCES = empty # 0b000 +SPD_SOURCES = ehlcrb # 0b000 diff --git a/src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex b/src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex new file mode 100644 index 0000000..71e5456 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 E1 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c index 11db732..8a2b8f9 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c @@ -5,4 +5,55 @@ #include <soc/meminit.h> #include <soc/romstage.h>
-/* ToDo : Fill EHL related memory configs */ +static const struct mb_cfg ehlcrb_lpddr4x_memcfg_cfg = { + + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = {3, 0, 1, 2, 7, 4, 5, 6}, + .dqs_map[DDR_CH1] = {3, 0, 1, 2, 7, 4, 5, 6}, + + /* Baseboard uses 100, 100 and 100 rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + .rcomp_targets = {60, 40, 30, 20, 30}, + + /* LPDDR4x does not allow interleaved memory */ + .dq_pins_interleaved = 0, + + /* Baseboard is using config 2 for vref_ca */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, + + /* Set Board Type */ + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memcfg_config(void) +{ + return &ehlcrb_lpddr4x_memcfg_cfg; +} diff --git a/src/soc/intel/elkhartlake/include/soc/meminit.h b/src/soc/intel/elkhartlake/include/soc/meminit.h index ea4664a..2dcbd13 100644 --- a/src/soc/intel/elkhartlake/include/soc/meminit.h +++ b/src/soc/intel/elkhartlake/include/soc/meminit.h @@ -88,11 +88,26 @@
/* * Rcomp target values. These will typically be the following - * values for Elkhart Lake : { 80, 40, 40, 40, 30 } + * values for Elkhart Lake : { 60, 40, 30, 20, 30 } */ uint16_t rcomp_targets[5];
/* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + uint8_t dq_pins_interleaved; + + /* + * VREF_CA configuration. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + uint8_t vref_ca_config; + + /* * Early Command Training Enable/Disable Control * 1 = enable, 0 = disable */ diff --git a/src/soc/intel/elkhartlake/meminit.c b/src/soc/intel/elkhartlake/meminit.c index cd777ba..f1f8270 100644 --- a/src/soc/intel/elkhartlake/meminit.c +++ b/src/soc/intel/elkhartlake/meminit.c @@ -109,6 +109,7 @@
/* Early Command Training Enabled */ mem_cfg->ECT = board_cfg->ect; - + mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; + mem_cfg->CaVrefConfig = board_cfg->vref_ca_config; mem_cfg->UserBd = board_cfg->UserBd; }
-
Lean Sheng Tan (Code Review) -
Werner Zeh (Code Review)