Lean Sheng Tan uploaded patch set #2 to this change.

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mb/intel/ehlcrb: Add EHL CRB memory initialization support

Update memory parameters based on memory type supported by
Elkhart Lake CRB:

1. Update spd data for EHL LPDDR4X memory
   - DQ byte map
   - DQS CPU-DRAM map
   - Rcomp resistor
   - Rcomp target
2. Add configurations for vref_ca & interleaved memory
3. Add EHL CRB on board LPDDR4X SPD data bin file
4. Update mainboard related FSPM UPDs as part of memory
   initialization

Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b
---
M src/mainboard/intel/elkhartlake_crb/romstage_fsp_params.c
M src/mainboard/intel/elkhartlake_crb/spd/Makefile.inc
A src/mainboard/intel/elkhartlake_crb/spd/ehlcrb.spd.hex
M src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/memory.c
M src/soc/intel/elkhartlake/include/soc/meminit.h
M src/soc/intel/elkhartlake/meminit.c
6 files changed, 114 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/48127/2

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