Change in ...coreboot[master]: soc/intel/cnl/acpi: add ish ACPI device

[Jett Rink (Code Review)]

Jett Rink has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31681

Change subject: soc/intel/cnl/acpi: add ish ACPI device
......................................................................

soc/intel/cnl/acpi: add ish ACPI device

Create the ISH ACPI device so we can hang fields off of a _DSD table.

Since this is also a PCI device that has run time probing, we can always
emit the ACPI device and let the device tree true the device on or off.

BRANCH=none
BUG=b:122722008
TEST=verify that _DSD table gets publish under ISH device in kernel ACPI
tables. Also verified that device is still turned off if device tree for
ISH is off.

Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2
Signed-off-by: Jett Rink 
---
A src/soc/intel/cannonlake/acpi/ish.asl
M src/soc/intel/cannonlake/acpi/southbridge.asl
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/31681/1

diff --git a/src/soc/intel/cannonlake/acpi/ish.asl b/src/soc/intel/cannonlake/acpi/ish.asl
new file mode 100644
index 0000000..8a724d3
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/ish.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Integrated Sensor Hub Controller 0:13.0 */
+
+Device (ISHB)
+{
+	Name (_ADR, 0x00130000)
+	Name (_DDN, "Integrated Sensor Hub Controller")
+}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index dfa2975..ae8de6a 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -51,6 +51,9 @@
 /* SMBus 0:1f.4 */
 #include "smbus.asl"

+/* ISH 0:13.0 */
+#include "ish.asl"
+
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"

[Jett Rink (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31681

to look at the new patch set (#2).

Change subject: soc/intel/cnl/acpi: add ish ACPI device
......................................................................

soc/intel/cnl/acpi: add ish ACPI device

Create the ISH ACPI device so we can hang fields off of a _DSD table.

Since this is also a PCI device that has run time probing, we can always
emit the ACPI device and let the device tree true the device on or off.

BRANCH=none
BUG=b:122722008
TEST=verify that _DSD table gets publish under ISH device in kernel ACPI
tables. Also verified that device is still turned off if device tree for
ISH is off.

Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2
Signed-off-by: Jett Rink 
---
A src/soc/intel/cannonlake/acpi/ish.asl
M src/soc/intel/cannonlake/acpi/southbridge.asl
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/31681/2

[Raul Rangel (Code Review)]

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31681 )

Change subject: soc/intel/cnl/acpi: add ish ACPI device
......................................................................

Patch Set 2: Code-Review+1

(1 comment)

https://review.coreboot.org/#/c/31681/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/31681/2//COMMIT_MSG@12 
PS2, Line 12: true
turn?

[Lijian Zhao (Code Review)]

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31681 )

Change subject: soc/intel/cnl/acpi: add ish ACPI device
......................................................................

Patch Set 2: Code-Review+2

[Jett Rink (Code Review)]

Hello Aaron Durbin, Patrick Rudolph, Lijian Zhao, build bot (Jenkins), Raul Rangel, Furquan Shaikh, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31681

to look at the new patch set (#3).

Change subject: soc/intel/cnl/acpi: add ish ACPI device
......................................................................

soc/intel/cnl/acpi: add ish ACPI device

Create the ISH ACPI device so we can hang fields off of a _DSD table.

Since this is also a PCI device that has run time probing, we can always
emit the ACPI device and let the device tree turn the device on or off.

BRANCH=none
BUG=b:122722008
TEST=verify that _DSD table gets publish under ISH device in kernel ACPI
tables. Also verified that device is still turned off if device tree for
ISH is off.

Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2
Signed-off-by: Jett Rink 
---
A src/soc/intel/cannonlake/acpi/ish.asl
M src/soc/intel/cannonlake/acpi/southbridge.asl
2 files changed, 25 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/31681/3

[Jett Rink (Code Review)]

Jett Rink has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31681 )

Change subject: soc/intel/cnl/acpi: add ish ACPI device
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/#/c/31681/2//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/#/c/31681/2//COMMIT_MSG@12 
PS2, Line 12: true
> turn?

Done

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31681 )

Change subject: soc/intel/cnl/acpi: add ish ACPI device
......................................................................

Patch Set 3: Code-Review+2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has removed a vote on this change.

Change subject: soc/intel/cnl/acpi: add ish ACPI device
......................................................................

Removed Code-Review+2 by Furquan Shaikh

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31681 )

Change subject: soc/intel/cnl/acpi: add ish ACPI device
......................................................................

soc/intel/cnl/acpi: add ish ACPI device

Create the ISH ACPI device so we can hang fields off of a _DSD table.

Since this is also a PCI device that has run time probing, we can always
emit the ACPI device and let the device tree turn the device on or off.

BRANCH=none
BUG=b:122722008
TEST=verify that _DSD table gets publish under ISH device in kernel ACPI
tables. Also verified that device is still turned off if device tree for
ISH is off.

Change-Id: Ic0231f1ac637fea0e251eb3ac84f0fd8d64c12b2
Signed-off-by: Jett Rink 
Reviewed-on: https://review.coreboot.org/c/31681
Reviewed-by: Raul Rangel 
Reviewed-by: Lijian Zhao 
Tested-by: build bot (Jenkins) 
---
A src/soc/intel/cannonlake/acpi/ish.asl
M src/soc/intel/cannonlake/acpi/southbridge.asl
2 files changed, 25 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Lijian Zhao: Looks good to me, approved
  Raul Rangel: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/cannonlake/acpi/ish.asl b/src/soc/intel/cannonlake/acpi/ish.asl
new file mode 100644
index 0000000..1c832b4
--- /dev/null
+++ b/src/soc/intel/cannonlake/acpi/ish.asl
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 Google LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Intel Integrated Sensor Hub Controller 0:13.0 */
+
+Device (ISHB)
+{
+	Name (_ADR, 0x00130000)
+	Name (_DDN, "Integrated Sensor Hub Controller")
+}
diff --git a/src/soc/intel/cannonlake/acpi/southbridge.asl b/src/soc/intel/cannonlake/acpi/southbridge.asl
index dfa2975..ae8de6a 100644
--- a/src/soc/intel/cannonlake/acpi/southbridge.asl
+++ b/src/soc/intel/cannonlake/acpi/southbridge.asl
@@ -51,6 +51,9 @@
 /* SMBus 0:1f.4 */
 #include "smbus.asl"

+/* ISH 0:13.0 */
+#include "ish.asl"
+
 /* USB XHCI 0:14.0 */
 #include "xhci.asl"