Change in coreboot[master]: soc/intel/tigerlake: Define TCSS AUX pin bias control

[Brandon Breitenstein (Code Review)]

Brandon Breitenstein has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47653 )

Change subject: soc/intel/tigerlake: Define TCSS AUX pin bias control
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/inc... 
File src/soc/intel/tigerlake/include/soc/early_tcss.h:

https://review.coreboot.org/c/coreboot/+/47653/1/src/soc/intel/tigerlake/inc... 
PS1, Line 103: 0x09000000
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for the GPIO pins this is how FSP has them defined and what it is expecting. see FspsUpd.h and reference the GpioPinsTGLH.h file in FSP