[M] Change in coreboot[master]: [TESTME] mb/google/kahlee/mainboard: rewrite IRQ mapping handling

[Felix Held (Code Review)]

Attention is currently required from: Jason Nien, Martin Roth.

Hello Jason Nien, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/68851

to look at the new patch set (#2).

Change subject: [TESTME] mb/google/kahlee/mainboard: rewrite IRQ mapping handling
......................................................................

[TESTME] mb/google/kahlee/mainboard: rewrite IRQ mapping handling

Rewrite the Kahlee IRQ mapping handling to be in line with the newer AMD
SoCs to allow making the largest part of the corresponding code common
for all AMD SoCs in the coreboot tree.

The PIC-mode IRQ numbers for both PIRQ_ASF and PIRQ_SDIO were 0 in the
data tables which is the PIT IRQ which looks very wrong to me, so it was
changed to PIRQ_NC. Since the ASF and likely also the SDIO controller
are unused, this shouldn't change runtime behavior. The data tables also
had non 0 and non 0x1f entries in the following locations the internal
BKDG #55072 revision 3.04 describes as unused: 0x31, 0x33, 0x35-0x37,
0x40, 0x50-0x53. The entry at 0x32 is also non 0 and non 0x1f and the
description in the BKDG says that it controls the IRQ mapping of another
internal PCI device, but that PCI device doesn't exist in the SoC.

Signed-off-by: Felix Held 
Change-Id: I9b3bfca33d88ef3989b63f4fe6c301e0e485b7e9
---
M src/mainboard/google/kahlee/mainboard.c
1 file changed, 88 insertions(+), 41 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/68851/2