[XS] Change in libgfxinit[cros]: gma tgl: Pcode CDCLK_PREPARE_FOR_CHANGE is not mandatory

[Dinesh Gehlot (Code Review)]

Attention is currently required from: Anil Kumar K, Jérémy Compostella.

Hello Anil Kumar K, Jérémy Compostella,

I'd like you to do a code review.
Please visit

https://review.coreboot.org/c/libgfxinit/+/82147?usp=email

to review the following change.

Change subject: gma tgl: Pcode CDCLK_PREPARE_FOR_CHANGE is not mandatory
......................................................................

gma tgl: Pcode CDCLK_PREPARE_FOR_CHANGE is not mandatory

Pcode mailbox `CDCLK_PREPARE_FOR_CHANGE' command is not available till
BIOS Reset CPL and may fail when called too early.

This command is actually not mandatory to set the CDCLK sucessfully on
ADL platform.  This patch keeps the `CDCLK_PREPARE_FOR_CHANGE' command
but ignores return errors if any.

Change-Id: I0514e404a7b580d1e35af7b39c1bd77183f11058
Signed-off-by: Jeremy Compostella 
Signed-off-by: Anil Kumar 
---
M common/tigerlake/hw-gfx-gma-power_and_clocks.adb
1 file changed, 5 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/47/82147/1

diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
index 68636f7..41331b9 100644
--- a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
+++ b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb
@@ -328,7 +328,7 @@
          Wait_Ready => True,
          Success    => Success);

-      if not Success then
+      if not Success and not Config.CPU_Alderlake then
          pragma Debug (Debug.Put_Line
                        ("ERROR: PCODE not ready for frequency change."));
          return;
@@ -348,7 +348,8 @@
          Registers.Wait_Set_Mask
            (Register  => Registers.CDCLK_PLL_ENABLE,
             Mask      => CDCLK_PLL_ENABLE_PLL_LOCK or
-                         CDCLK_PLL_ENABLE_FREQ_REQ_ACK);
+                         CDCLK_PLL_ENABLE_FREQ_REQ_ACK,
+            Success  => Success);
          Registers.Write
            (Register => Registers.CDCLK_PLL_ENABLE,
             Value    => Word32(PLL_Ratio) or
@@ -413,7 +414,8 @@
          Command  => (if    CDClk <= 312_000_000 then 0
                       elsif CDClk <= 326_400_000 then 1
                       elsif CDClk <= 556_800_000 then 2
-                      else 3));
+                      else 3),
+         Wait_Ready => True);
       Config.CDClk := CDClk;
    end Set_CDClk;