Change in coreboot[master]: mb/google/guybrush/var/guybrush: Add FPMCU configration

[Ivy Jian (Code Review)]

Ivy Jian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/52181 )

Change subject: mb/google/guybrush/var/guybrush: Add FPMCU configration
......................................................................

mb/google/guybrush/var/guybrush: Add FPMCU configration

Enable CRFP in devicetree.
Update gpios for FPMCU power ready.

BUG=b:182201937
BRANCH=None
TEST=Boot into OS then FPMCU is responding.

Signed-off-by: Ivy Jian 
Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59
---
M src/mainboard/google/guybrush/Kconfig
M src/mainboard/google/guybrush/mainboard.c
M src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/guybrush/variants/guybrush/Makefile.inc
M src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
A src/mainboard/google/guybrush/variants/guybrush/variant.c
6 files changed, 42 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/52181/1

diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig
index 9f43d5e..84b6a1d 100644
--- a/src/mainboard/google/guybrush/Kconfig
+++ b/src/mainboard/google/guybrush/Kconfig
@@ -28,6 +28,7 @@
    select MAINBOARD_HAS_TPM2
    select SOC_AMD_CEZANNE
    select SOC_AMD_COMMON_BLOCK_USE_ESPI
+	select DRIVERS_UART_ACPI

config CHROMEOS
    select EC_GOOGLE_CHROMEEC_SWITCHES
diff --git a/src/mainboard/google/guybrush/mainboard.c b/src/mainboard/google/guybrush/mainboard.c
index 57f658c..f26784a 100644
--- a/src/mainboard/google/guybrush/mainboard.c
+++ b/src/mainboard/google/guybrush/mainboard.c
@@ -102,6 +102,7 @@
 {
    mainboard_configure_gpios();
    mainboard_ec_init();
+	variant_fpmcu_init();
 }

static void mainboard_enable(struct device *dev)
@@ -115,6 +116,11 @@
    pirq_setup();
 }

+void __weak variant_fpmcu_init(void)
+{
+        /* Default weak implementation */
+}
+
 struct chip_operations mainboard_ops = {
    .init = mainboard_init,
    .enable_dev = mainboard_enable,
diff --git a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
index dccaed0..afac157 100644
--- a/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/guybrush/variants/baseboard/include/baseboard/variants.h
@@ -24,4 +24,7 @@
 /* This function provides GPIO settings before entering sleep. */
 const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size);

+/* FPCMU power init*/
+void variant_fpmcu_init(void);
+
 #endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc
index 88e75bd..82fe6f5 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc
+++ b/src/mainboard/google/guybrush/variants/guybrush/Makefile.inc
@@ -1,3 +1,5 @@
 # SPDX-License-Identifier: GPL-2.0-or-later

subdirs-y += ./memory
+ramstage-y += variant.c
+
diff --git a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
index 707a63f..dc1f211 100644
--- a/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/guybrush/overridetree.cb
@@ -98,4 +98,17 @@
    	end
    end # I2C2

+        device mmio 0xfedca000 on
+                chip drivers/uart/acpi
+                        register "name" = ""CRFP""
+                        register "desc" = ""Fingerprint Reader""
+                        register "hid" = "ACPI_DT_NAMESPACE_HID"
+                        register "compat_string" = ""google,cros-ec-uart""
+                        register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_21)"
+                        register "wake" = "GEVENT_5"
+                        register "uart" = "ACPI_UART_RAW_DEVICE(3000000, 64)"
+                        device generic 0 on end
+                end
+        end
+
 end	# chip soc/amd/cezanne
diff --git a/src/mainboard/google/guybrush/variants/guybrush/variant.c b/src/mainboard/google/guybrush/variants/guybrush/variant.c
new file mode 100644
index 0000000..eacf550
--- /dev/null
+++ b/src/mainboard/google/guybrush/variants/guybrush/variant.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <delay.h>
+#include <gpio.h>
+#include <baseboard/variants.h>
+#include <soc/gpio.h>
+
+void variant_fpmcu_init(void)
+{
+       /*
+       * Enable the FPMCU by enabling EN_PWR_FP, then bringing it out
+       * of reset by setting FPMCU_RST_L high 3ms later.
+       */
+       gpio_set(GPIO_32, 1);
+       mdelay(3);
+       gpio_set(GPIO_11, 1);
+}