Change in ...coreboot[master]: soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug fro...
Jeremy Soller has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31535
Change subject: soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree ......................................................................
soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree
Change-Id: I3aa8990a335e413628c016007ebabf7142aef80d --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31535/1
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index cb9ad38..71e6f52 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -162,6 +162,8 @@ uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; /* PCIe LTR(Latency Tolerance Reporting) mechanism */ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* Enable/Disable HotPlug support for Root Port */ + uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
/* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c276c86..2107610 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -181,6 +181,8 @@ sizeof(config->PcieClkSrcClkReq)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(config->PcieRpLtrEnable)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, + sizeof(config->PcieRpHotPlug));
/* eMMC and SD */ dev = dev_find_slot(0, PCH_DEVFN_EMMC);
Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31535
to look at the new patch set (#2).
Change subject: soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree ......................................................................
soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree
Tested on system76 galp3-c
Signed-off-by: Jeremy Soller jeremy@system76.com Change-Id: I3aa8990a335e413628c016007ebabf7142aef80d --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/31535/2
Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31535 )
Change subject: soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree ......................................................................
Patch Set 2: Code-Review+2
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31535 )
Change subject: soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31535/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31535/2//COMMIT_MSG@7 PS2, Line 7: soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree A little shorter:
Support setting FSP-S PcieRpHotPlug from devicetree
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31535 )
Change subject: soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree ......................................................................
soc/intel/cannonlake: Add support for setting FSP-S PcieRpHotPlug from devicetree
Tested on system76 galp3-c
Signed-off-by: Jeremy Soller jeremy@system76.com Change-Id: I3aa8990a335e413628c016007ebabf7142aef80d Reviewed-on: https://review.coreboot.org/c/31535 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 4 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved
diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 1f26f1e..ab7c765 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -162,6 +162,8 @@ uint8_t PcieClkSrcClkReq[CONFIG_MAX_ROOT_PORTS]; /* PCIe LTR(Latency Tolerance Reporting) mechanism */ uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; + /* Enable/Disable HotPlug support for Root Port */ + uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
/* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index a198f1b..17a014b 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -188,6 +188,8 @@ sizeof(config->PcieClkSrcClkReq)); memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(config->PcieRpLtrEnable)); + memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, + sizeof(config->PcieRpHotPlug));
/* eMMC and SD */ dev = dev_find_slot(0, PCH_DEVFN_EMMC);
-
Furquan Shaikh (Code Review) -
Jeremy Soller (Code Review)
-
Patrick Georgi (Code Review)
-
Paul Menzel (Code Review)