Patch set updated for coreboot: intel/skylake: Add support to enable wake-on-usb attach/detach
Furquan Shaikh (furquan@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17056
-gerrit
commit c20e4b714259c419efc99c698b6a59d937addf34 Author: Furquan Shaikh furquan@chromium.org Date: Tue Oct 18 14:25:25 2016 -0700
intel/skylake: Add support to enable wake-on-usb attach/detach
Three things are required to enable wake-on-usb: 1. 5V to USB ports should be enabled in S3. 2. ASL file needs to have appropriate wake bit set. 3. XHCI controller should have the wake on attach/detach bit set for the corresponding port in PORTSCN register.
Only part missing was #3.
This CL adds support to allow mainboard to define a bitmap in devicetree corresponding to the ports that it wants to enable wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in PORTSCN would be set by xhci.asl for the appropriate ports.
BUG=chrome-os-partner:58734 BRANCH=None TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb attach/detach.
Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf Signed-off-by: Furquan Shaikh furquan@chromium.org --- src/soc/intel/skylake/acpi.c | 2 ++ src/soc/intel/skylake/acpi/globalnvs.asl | 1 + src/soc/intel/skylake/acpi/xhci.asl | 37 ++++++++++++++++++++++++++++++++ src/soc/intel/skylake/chip.h | 3 +++ src/soc/intel/skylake/include/soc/nvs.h | 3 ++- src/soc/intel/skylake/include/soc/usb.h | 2 ++ 6 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 28a0a6e..b839b75 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -198,6 +198,8 @@ static void acpi_create_gnvs(global_nvs_t *gnvs)
/* Fill in the Wifi Region id */ gnvs->cid1 = wifi_regulatory_domain(); + + gnvs->uweb = config->usb_wake_enable_bitmap; }
unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 2bff7d3..6d95f0f 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -64,6 +64,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) NHLA, 64, // 0x31 - NHLT Address NHLL, 32, // 0x39 - NHLT Length CID1, 16, // 0x3d - Wifi Country Identifier + UWEB, 16, // 0x3f - USB Wake Enable Bitmap
/* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 1a1c6e3..cab23e1 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -15,6 +15,30 @@ * GNU General Public License for more details. */
+/* + * Enable wake-up on USB attach/detach for given port. + * Arg0 - Port Number + * Arg1 - XHCI Memory-mapped address + */ +Method (UPWE, 2, Serialized) +{ + /* + * PORTSCN starts at offset 0x480 for port 1, 0x490 for port 2 and so + * on. Get the region base address by using port number. + */ + Add (0x480, Multiply (Subtract (Arg0, 1), 0x10), Local0) + OperationRegion (PSCN, SystemMemory, + Add (ShiftLeft (Arg1, 16), Local0), 0x10) + Field (PSCN, AnyAcc, NoLock, Preserve) + { + , 25, + UPCE, 1, + UPDE, 1, + } + Store (One, UPCE) + Store (One, UPDE) +} + /* XHCI Controller 0:14.0 */
Device (XHCI) @@ -26,6 +50,19 @@ Device (XHCI) Method (_DSW, 3) { Store (Arg0, PMEE) + + /* Get USB Wake enable bitmask. Take only lower 10 bits. */ + Store (\UWEB, Local0) + And (Local0, 0x3FF, Local0) + + While (One) { + FindSetRightBit (Local0, Local1) + If (LEqual (Local1, Zero)) { + Break + } + UPWE (Local1, XMEM) + Store (And (Local0, Subtract (Local0, 1)), Local0) + } }
Name (_S3D, 3) /* D3 supported in S3 */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 00393b2..ed9b8d4 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -395,6 +395,9 @@ struct soc_intel_skylake_config {
/* Use custom SD card detect GPIO configuration */ struct acpi_gpio sdcard_cd_gpio; + + /* Wake Enable Bitmap for USB ports */ + u16 usb_wake_enable_bitmap; };
typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index f9d5b71..f89f82b 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -54,7 +54,8 @@ typedef struct { u64 nhla; /* 0x31 - NHLT Address */ u32 nhll; /* 0x39 - NHLT Length */ u16 cid1; /* 0x3d - Wifi Country Identifier */ - u8 unused[193]; + u16 uweb; /* 0x3f - USB Wake Enable Bitmap */ + u8 unused[191];
/* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h index e5b0495..f837366 100644 --- a/src/soc/intel/skylake/include/soc/usb.h +++ b/src/soc/intel/skylake/include/soc/usb.h @@ -169,4 +169,6 @@ struct usb3_port_config { .tx_downscale_amp = 0x00, \ }
+#define USB2_PORT(x) (1 << (x - 1)) + #endif
-
Furquan Shaikh