Change in coreboot[master]: soc/intel/common: Add compressed ME_RW blobs to ME_RW_A/B for ADL-N

[Tim Wawrzynczak (Code Review)]

Attention is currently required from: Reka Norman, Jamie Ryu, Wonkyu Kim, Subrata Banik, Kangheui Won, Ravishankar Sarawadi, Rizwan Qureshi, Balaji Manigandan, Krishna P Bhat D, Nick Vaccaro, Patrick Rudolph, EricR Lai.
Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62358 )

Change subject: soc/intel/common: Add compressed ME_RW blobs to ME_RW_A/B for ADL-N
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Patch Set 2:

(1 comment)

File src/soc/intel/common/block/cse/Makefile.inc:

https://review.coreboot.org/c/coreboot/+/62358/comment/c8fbaf8a_87fcc7a0 
PS2, Line 88: ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y)
> Will this impact the ADL-P? If we don't touch the flashmap.md just reduce the size, should be fine. […]

Agreed, would rather add a kconfig like

```
config SOC_INTEL_CSE_LITE_COMPRESS_ME_RW
        bool
        default n
        depends on SOC_INTEL_CSE_LITE_SKU
        help.....
```

and then Nissa can select it.