Change in coreboot[master]: soc/intel/common: Use heci_reset() in the CSE TX and RX flows

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Patrick Rudolph.
Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62587 )

Change subject: soc/intel/common: Use heci_reset() in the CSE TX and RX flows
......................................................................

soc/intel/common: Use heci_reset() in the CSE TX and RX flows

The patch implements error handling as per the ME BWG guide. The BWG
recommends HECI interface reset if there is timeout  or malformed
response is received. Also, the patch triggers HECI interface reset
if cse link state is not ready in heci_send() API.

TEST=Verify HECI Interface reset in the simulated error scenarios.

Signed-off-by: Sridhar Siricilla 
Change-Id: I3e4a97800cbc5d95b8fd259e6e34a32fc82d8563
---
M src/soc/intel/common/block/cse/cse.c
1 file changed, 6 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62587/1

diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c
index a16521c..17fd661 100644
--- a/src/soc/intel/common/block/cse/cse.c
+++ b/src/soc/intel/common/block/cse/cse.c
@@ -458,6 +458,8 @@
    		return CSE_TX_RX_SUCCESS;
    }

+	printk(BIOS_DEBUG, "HECI: Trigger HECI reset\n");
+	heci_reset();
    return CSE_TX_ERR_CSE_NOT_READY;
 }

@@ -548,7 +550,7 @@
    		ret = recv_one_message(&hdr, p, left, &received);
    		if (ret) {
    			printk(BIOS_ERR, "HECI: Failed to receive!\n");
-				return ret;
+				goto CSE_RX_ERR_HANDLE;
    		}
    		left -= received;
    		p += received;
@@ -563,6 +565,9 @@
    	}
    }

+CSE_RX_ERR_HANDLE:
+	printk(BIOS_DEBUG, "HECI: Trigger HECI Reset\n");
+	heci_reset();
    return ret;
 }