[XS] Change in coreboot[main]: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume

[Jonathon Hall (Code Review)]

Attention is currently required from: Bill XIE.

Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78288?usp=email )

Change subject: drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume
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Patch Set 4: Code-Review+2

(1 comment)

Patchset:

PS4: 
Agree, we shouldn't reset CMOS during S3 resume.

@Bill, does this also mean that X200 with CONFIG(STATIC_OPTION_TABLE) now performs memory training on every boot, since a normal boot will still erase training data?

Perhaps there should be some way to not erase that range, such as only erasing bits/bytes covered by a checksum when restoring CMOS defaults.  The X200 memory training data (as well as something for VBOOT) are not included in the checksum.  Seems this would also work nicely with the RTC clock data, which are currently excluded by starting from offset 14 here.