Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41945 )
Change subject: sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits ......................................................................
sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits
Commit 73ae076 "fixed" accesses to the PCI command register that were not 16 bits, but also lost some bits to be written in the process.
Change-Id: I4eb62a0433a4563827a69c9e39c17ddd2eb8cd23 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/lynxpoint/early_usb.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/serialio.c 3 files changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/41945/1
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index 86abbe0..313d0c2 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -24,7 +24,7 @@ static void enable_usb_bar_on_device(pci_devfn_t dev, u32 bar) { pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); }
void enable_usb_bar(void) diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 79d47da..ebe0aa9 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -730,7 +730,7 @@ mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index accc51b..a75cea0 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -137,7 +137,7 @@ printk(BIOS_DEBUG, "Initializing Serial IO device\n");
/* Ensure memory and bus master are enabled */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41945 )
Change subject: sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits ......................................................................
Patch Set 2: Code-Review+2
Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41945 )
Change subject: sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits ......................................................................
Patch Set 2: Code-Review+2
Angel Pons has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/41945 )
Change subject: sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits ......................................................................
Removed Verified+1 by build bot (Jenkins) no-reply@coreboot.org
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41945 )
Change subject: sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits ......................................................................
sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits
Commit 73ae076 "fixed" accesses to the PCI command register that were not 16 bits, but also lost some bits to be written in the process.
Change-Id: I4eb62a0433a4563827a69c9e39c17ddd2eb8cd23 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41945 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr Reviewed-by: Matt DeVillier matt.devillier@gmail.com --- M src/southbridge/intel/lynxpoint/early_usb.c M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/serialio.c 3 files changed, 3 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved Matt DeVillier: Looks good to me, approved
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c index 06ddd08..a753681 100644 --- a/src/southbridge/intel/lynxpoint/early_usb.c +++ b/src/southbridge/intel/lynxpoint/early_usb.c @@ -25,7 +25,7 @@ static void enable_usb_bar_on_device(pci_devfn_t dev, u32 bar) { pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); }
void enable_usb_bar(void) diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 8914edf..6223a3d 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -735,7 +735,7 @@ mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index e093508..adb9067 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -137,7 +137,7 @@ printk(BIOS_DEBUG, "Initializing Serial IO device\n");
/* Ensure memory and bus master are enabled */ - pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
/* Find BAR0 and BAR1 */ bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41945 )
Change subject: sb/intel/lynxpoint: Restore lost PCI_COMMAND_MASTER bits ......................................................................
Patch Set 4:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4475 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4474 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4473 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4472
Please note: This test is under development and might not be accurate at all!
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9elements QA (Code Review) -
Angel Pons (Code Review)
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HAOUAS Elyes (Code Review)
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Matt DeVillier (Code Review)