[XS] Change in coreboot[main]: mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC

[Jérémy Compostella (Code Review)]

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87505?usp=email )

Change subject: mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC
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mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC

This commit addresses a performance issue on the Panther Lake H SoC by
disabling the EnableFastVmode setting in addition to the CepEnable
setting. It was discovered that merely disabling CepEnable was
insufficient, as the FSP continued to program IccLimit, causing performance
degradation under high-stress conditions. By also disabling
EnableFastVmode, the I_TRIP value is prevented from being set lower than
the device's actual capability.

TEST=Verified that IccLimit limit is not programmed at all in the FSP logs.

Change-Id: I2974f1311b69f283d7fa4982c28a9037a8ab23f7
Signed-off-by: Jeremy Compostella 
---
M src/mainboard/google/fatcat/romstage.c
1 file changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/87505/1

diff --git a/src/mainboard/google/fatcat/romstage.c b/src/mainboard/google/fatcat/romstage.c
index 44a901a..7a50938 100644
--- a/src/mainboard/google/fatcat/romstage.c
+++ b/src/mainboard/google/fatcat/romstage.c
@@ -62,8 +62,10 @@
     * because the I_TRIP value is set lower than the device's actual capability.
     */
    printk(BIOS_INFO, "Disabling VR settings on PTL-H.\n");
-	for (size_t i = 0; i < NUM_VR_DOMAINS; i++)
+	for (size_t i = 0; i < NUM_VR_DOMAINS; i++) {
    	m_cfg->CepEnable[i] = false;
+		m_cfg->EnableFastVmode[i] = false;
+	}
 }

void mainboard_memory_init_params(FSPM_UPD *memupd)