Change in coreboot[master]: soc/intel/alderlake: Update USB2_PORT_MAX macro

[Sridhar Siricilla (Code Review)]

Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph.
Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61623 )

Change subject: soc/intel/alderlake: Update USB2_PORT_MAX macro
......................................................................

soc/intel/alderlake: Update USB2_PORT_MAX macro

The patch updates USB2_PORT_MAX macro to allow mark type_c flag and
also also renames the macro to USB2_PORT_MAX_TYPE_C to reflect the USB2
port is mapped to Type-C.

BUG=b:193287279
TEST=Build the Gimble board

Signed-off-by: Sridhar Siricilla 
Change-Id: I464f139d8e367907191c04f9170ac53d327776ee
---
M src/soc/intel/alderlake/include/soc/usb.h
1 file changed, 3 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/61623/1

diff --git a/src/soc/intel/alderlake/include/soc/usb.h b/src/soc/intel/alderlake/include/soc/usb.h
index 70a367e..0d19a13 100644
--- a/src/soc/intel/alderlake/include/soc/usb.h
+++ b/src/soc/intel/alderlake/include/soc/usb.h
@@ -94,14 +94,15 @@
    .pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
 }

-/* Max TX and Pre-emp settings */
-#define USB2_PORT_MAX(pin) { \
+/* Type-C Port, Max TX and Pre-emp settings */
+#define USB2_PORT_MAX_TYPE_C(pin) { \
    .enable        = 1, \
    .ocpin         = (pin), \
    .tx_bias       = USB2_BIAS_56P3MV, \
    .tx_emp_enable = USB2_PRE_EMP_ON, \
    .pre_emp_bias  = USB2_BIAS_56P3MV, \
    .pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+	.type_c        = 1, \
 }

/* Type-C Port, no BC1.2 charge detect module / MUX