Change in coreboot[master]: soc/intel/common/block/smm: Add delay(configurable) before entering S5

[Furquan Shaikh (Code Review)]

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/24964

Change subject: soc/intel/common/block/smm: Add delay(configurable) before entering S5
......................................................................

soc/intel/common/block/smm: Add delay(configurable) before entering S5

This change adds a configurable delay in milliseconds before SLP_EN is
set in SLP_SMI for S5. Reason for doing this is to avoid race between
SLP and power button SMIs.

On some platforms (Nami, Nautilus), it was observed that power button
SMI triggered by EC was competing with the SLP SMI triggered by
keyboard driver. Keyboard driver indicated power button press which
resulted in depthcharge triggering SLP_SMI, causing the AP to enter
S5. However, the power button press also causes the EC to send a pulse
on PWRBTN# line, which is debounced for 16ms before an interrupt is
triggered. This interrupt was generated after SLP_SMI is processed
which resulted in the device waking back up from S5.

This change adds a config option
SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS which is used to add a delay
before SLP_EN is set for S5. This change should only affect CHROMEOS
boards as the config option will be 0 in other cases.

BUG=b:74083107
TEST=Verified that nami, nautilus do not wake back from S5 on power
button press at dev mode screen.

Change-Id: Iaee19b5aba0aad7eb34bd126fda5b0f6ef394ed7
Signed-off-by: Furquan Shaikh 
---
M src/soc/intel/common/block/smm/Kconfig
M src/soc/intel/common/block/smm/smihandler.c
2 files changed, 14 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/24964/1

diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig
index 0355780..909382e 100644
--- a/src/soc/intel/common/block/smm/Kconfig
+++ b/src/soc/intel/common/block/smm/Kconfig
@@ -7,3 +7,12 @@
    bool
    help
      Intel Processor trap flag if it is supported
+
+config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS
+	int
+	default 100 if CHROMEOS
+	default 0
+	help
+	  Time in milliseconds that SLP_SMI for S5 waits for before
+	  enabling sleep. This is required to avoid any race between
+	  SLP_SMI and PWRBTN SMI.
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c
index 81ff3eb..fc908c2 100644
--- a/src/soc/intel/common/block/smm/smihandler.c
+++ b/src/soc/intel/common/block/smm/smihandler.c
@@ -19,6 +19,7 @@
 #include <console/console.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
+#include <delay.h>
 #include <device/pci_def.h>
 #include <elog.h>
 #include <intelblocks/fast_spi.h>
@@ -219,6 +220,10 @@
    	pmc_soc_restore_power_failure();
    	/* also iterates over all bridges on bus 0 */
    	busmaster_disable_on_bus(0);
+
+		mdelay(CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS);
+		pmc_clear_pm1_status();
+
    	break;
    default:
    	printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");