Change in coreboot[master]: soc/intel: Allow enable/disable ME via CMOS - coreboot-gerrit

3 Jun 2021


      Attention is currently required from: Andy Pont, Tim Wawrzynczak, Paul Menzel, Arthur Heymans, Patrick Rudolph.
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52800 )
Change subject: soc/intel: Allow enable/disable ME via CMOS
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Patch Set 25:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-120620):
https://review.coreboot.org/c/coreboot/+/52800/comment/b080f7b9_8a32cbf6 
PS25, Line 903: 		else
suspect code indent for conditional statements (16, 8)
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
Gerrit-Change-Number: 52800
Gerrit-PatchSet: 25
Gerrit-Owner: Sean Rhodes admin@starlabs.systems
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