Patch set updated for coreboot: ad5fc43 chromeec: allow override of i8042 interrupt

[Aaron Durbin]

Aaron Durbin ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4978

-gerrit

commit ad5fc4393051bb6fe35afcdbd285779927d2b0e4
Author: Aaron Durbin 
Date:   Wed Nov 20 15:18:24 2013 -0600

chromeec: allow override of i8042 interrupt

Some boards need to override which IRQ the i8042 keyboard
    controller has its interrupt on instead of the default
    IRQ#1. The SIO_EC_PS2K_IRQ macro provides the mainboard
    an ability to override the interrupt location.

BUG=chrome-os-partner:23965
    BRANCH=None
    TEST=Built and booted rambi using this option. New IRQ is correctly
         picked up by kernel allowing keyboard support.

Change-Id: Ic2b222018dfc3aa30e24a31009e832ae0fb7e9cf
    Reviewed-on: https://chromium-review.googlesource.com/177222
    Tested-by: Bernie Thompson 
    Reviewed-by: Aaron Durbin 
    Signed-off-by: Aaron Durbin 
    Tested-by: Aaron Durbin 
    Commit-Queue: Aaron Durbin 
---
 src/ec/google/chromeec/acpi/superio.asl | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl
index 5940181..a022864 100644
--- a/src/ec/google/chromeec/acpi/superio.asl
+++ b/src/ec/google/chromeec/acpi/superio.asl
@@ -152,7 +152,11 @@ Device (SIO) {
    	{
    		IO (Decode16, 0x60, 0x60, 0x01, 0x01)
    		IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+#ifdef SIO_EC_PS2K_IRQ
+			SIO_EC_PS2K_IRQ
+#else
    		IRQNoFlags () {1}
+#endif
    	})

Name (_PRS, ResourceTemplate()
@@ -160,7 +164,11 @@ Device (SIO) {
    		StartDependentFn (0, 0) {
    			IO (Decode16, 0x60, 0x60, 0x01, 0x01)
    			IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+#ifdef SIO_EC_PS2K_IRQ
+				SIO_EC_PS2K_IRQ
+#else
    			IRQNoFlags () {1}
+#endif
    		}
    		EndDependentFn ()
    	})