Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27331
Change subject: src: Get rid of non-local header treated as local ......................................................................
src: Get rid of non-local header treated as local
Change-Id: I2c5edadfd035c9af08af9ee326a5a2dc8b840faa Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/amd/car/post_cache_as_ram.c M src/cpu/amd/family_10h-family_15h/model_10xxx_init.c M src/cpu/intel/haswell/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl M src/mainboard/asus/kcma-d8/dsdt.asl M src/mainboard/asus/kfsn4-dre/dsdt.asl M src/mainboard/asus/kgpe-d16/dsdt.asl M src/mainboard/asus/p2b-ls/dsdt.asl M src/mainboard/asus/p2b/dsdt.asl M src/southbridge/intel/fsp_rangeley/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c 11 files changed, 26 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/27331/1
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 2fb46d2..32ea166 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -31,7 +31,7 @@ #include "cpu/amd/car/disable_cache_as_ram.c"
// For set_sysinfo_in_ram() -#include "northbridge/amd/amdfam10/raminit.h" +#include <northbridge/amd/amdfam10/raminit.h>
#if CONFIG_RAMTOP <= 0x100000 #error "You need to set CONFIG_RAMTOP greater than 1M" diff --git a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c index 562a267..4602de9 100644 --- a/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c +++ b/src/cpu/amd/family_10h-family_15h/model_10xxx_init.c @@ -24,7 +24,7 @@ #include <cpu/x86/pae.h> #include <pc80/mc146818rtc.h> #include <cpu/x86/lapic.h> -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include <cpu/amd/model_10xxx_rev.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> @@ -97,6 +97,7 @@ enable_cache();
/* Set up other MTRRs */ + amd_setup_mtrrs(); } else { while (!fam15h_startup_flags[id.nodeid][id.coreid - 1]) { diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 0e91dae..a26b549 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -38,10 +38,10 @@ #include <ec/google/chromeec/ec.h> #endif #include "haswell.h" -#include "northbridge/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/me.h" +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/me.h> #include <security/tpm/tspi.h> #include <cpu/intel/romstage.h>
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl b/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl index 54ead92..f8709a4 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl +++ b/src/mainboard/amd/serengeti_cheetah_fam10/dsdt.asl @@ -230,5 +230,5 @@ Z00A, 8 }
- #include "northbridge/amd/amdfam10/amdfam10_util.asl" + #include <northbridge/amd/amdfam10/amdfam10_util.asl> } diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl index 5754d7c..b6dd211 100644 --- a/src/mainboard/asus/kcma-d8/dsdt.asl +++ b/src/mainboard/asus/kcma-d8/dsdt.asl @@ -39,8 +39,8 @@ 0x00000001 /* OEM Revision */ ) { - #include "northbridge/amd/amdfam10/amdfam10_util.asl" - #include "southbridge/amd/sr5650/acpi/sr5650.asl" + #include <northbridge/amd/amdfam10/amdfam10_util.asl> + #include <southbridge/amd/sr5650/acpi/sr5650.asl>
/* Some global data */ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ @@ -427,7 +427,7 @@ { Name (_ADR, 0x00110000) // _ADR: Address Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include "southbridge/amd/sb700/acpi/sata.asl" + #include <southbridge/amd/sb700/acpi/sata.asl> }
/* 0:12.0 SP5100 USB 0 */ @@ -477,7 +477,7 @@ { Name (_ADR, 0x00140001) // _ADR: Address Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include "southbridge/amd/sb700/acpi/ide.asl" + #include <southbridge/amd/sb700/acpi/ide.asl> }
/* 0:14.3 SP5100 LPC */ diff --git a/src/mainboard/asus/kfsn4-dre/dsdt.asl b/src/mainboard/asus/kfsn4-dre/dsdt.asl index 575715c..f3d59ce 100644 --- a/src/mainboard/asus/kfsn4-dre/dsdt.asl +++ b/src/mainboard/asus/kfsn4-dre/dsdt.asl @@ -39,7 +39,7 @@ 0x00000001 /* OEM Revision */ ) { - #include "northbridge/amd/amdfam10/amdfam10_util.asl" + #include <northbridge/amd/amdfam10/amdfam10_util.asl>
/* Some global data */ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ @@ -404,7 +404,7 @@ Return (Local3) }
-#include "southbridge/nvidia/ck804/acpi/ck804.asl" +#include <southbridge/nvidia/ck804/acpi/ck804.asl>
/* PCI Routing Table Access */ Method (_PRT, 0, NotSerialized) { diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index ab6547c..7b78b5d 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -39,8 +39,8 @@ 0x00000001 /* OEM Revision */ ) { - #include "northbridge/amd/amdfam10/amdfam10_util.asl" - #include "southbridge/amd/sr5650/acpi/sr5650.asl" + #include <northbridge/amd/amdfam10/amdfam10_util.asl> + #include <southbridge/amd/sr5650/acpi/sr5650.asl>
/* Some global data */ Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ @@ -427,7 +427,7 @@ { Name (_ADR, 0x00110000) // _ADR: Address Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include "southbridge/amd/sb700/acpi/sata.asl" + #include <southbridge/amd/sb700/acpi/sata.asl> }
/* 0:12.0 SP5100 USB 0 */ @@ -477,7 +477,7 @@ { Name (_ADR, 0x00140001) // _ADR: Address Name(_PRW, Package () {0x05, 0x04}) // Wake from S1-S4 - #include "southbridge/amd/sb700/acpi/ide.asl" + #include <southbridge/amd/sb700/acpi/ide.asl> }
/* 0:14.3 SP5100 LPC */ diff --git a/src/mainboard/asus/p2b-ls/dsdt.asl b/src/mainboard/asus/p2b-ls/dsdt.asl index 304a0f4..73d9508 100644 --- a/src/mainboard/asus/p2b-ls/dsdt.asl +++ b/src/mainboard/asus/p2b-ls/dsdt.asl @@ -116,7 +116,7 @@ Return (0x0B) } } - #include "southbridge/intel/i82371eb/acpi/intx.asl" + #include <southbridge/intel/i82371eb/acpi/intx.asl>
PCI_INTX_DEV(LNKA, _SB.PCI0.PX40.PIRA, 1) PCI_INTX_DEV(LNKB, _SB.PCI0.PX40.PIRB, 2) @@ -174,7 +174,7 @@ Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },
}) - #include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl" + #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl>
/* Begin southbridge block */ Device (PX40) @@ -230,7 +230,7 @@ Return (BUF1) } } - #include "southbridge/intel/i82371eb/acpi/i82371eb.asl" + #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> } Device (PX43) { diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index 8ddbf28..93f6afe 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -112,7 +112,7 @@ Return (0x0B) } } - #include "southbridge/intel/i82371eb/acpi/intx.asl" + #include <southbridge/intel/i82371eb/acpi/intx.asl>
PCI_INTX_DEV(LNKA, _SB.PCI0.PX40.PIRA, 1) PCI_INTX_DEV(LNKB, _SB.PCI0.PX40.PIRB, 2) @@ -160,7 +160,7 @@ Package (0x04) { 0x000CFFFF, 3, LNKD, 0 },
}) - #include "northbridge/intel/i440bx/acpi/sb_pci0_crs.asl" + #include <northbridge/intel/i440bx/acpi/sb_pci0_crs.asl>
/* Begin southbridge block */ Device (PX40) @@ -216,7 +216,7 @@ Return (BUF1) } } - #include "southbridge/intel/i82371eb/acpi/i82371eb.asl" + #include <southbridge/intel/i82371eb/acpi/i82371eb.asl> } Device (PX43) { diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 74df691..2f598d8 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <program_loading.h> -#include "northbridge/intel/fsp_rangeley/northbridge.h" +#include <northbridge/intel/fsp_rangeley/northbridge.h> #include "southbridge/intel/fsp_rangeley/soc.h" #include "southbridge/intel/fsp_rangeley/gpio.h" #include "southbridge/intel/fsp_rangeley/romstage.h" diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index cb4bc7e..4c45613 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -27,7 +27,7 @@ #if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #include "lp_gpio.h" #else -#include "southbridge/intel/common/gpio.h" +#include <southbridge/intel/common/gpio.h> #endif
const struct rcba_config_instruction pch_early_config[] = {
-
Elyes HAOUAS (Code Review)