New patch to review for coreboot: 0da4bd9 urara: UART: line control setting configuration added: 8bit, 1 stop bit, no parity

[Stefan Reinauer]

Stefan Reinauer ([e-mail]) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9185

-gerrit

commit 0da4bd9e6829a70e90ad85e620c0a659a6f56954
Author: Ionela Voinescu 
Date:   Thu Oct 30 14:49:53 2014 +0000

urara: UART: line control setting configuration added: 8bit, 1 stop bit, no parity

BUG=chrome-os-partner:31438
    TEST=built urara bootblock and ran it on the Pistachio FPGA, observed
          expected console output.
    BRANCH=none

Change-Id: Iface623f0b267f851e6d162d0321d56e3713a785
    Signed-off-by: Stefan Reinauer 
    Original-Commit-Id: 4122ae983dba907c10d0d0980863ae7bf94eda5e
    Original-Change-Id: I14fe343c98b11774b93b2724b6bffa3b45ea17b4
    Original-Signed-off-by: Ionela Voinescu 
    Original-Reviewed-on: https://chromium-review.googlesource.com/226551
    Original-Reviewed-by: Vadim Bendebury 
    Original-Commit-Queue: Vadim Bendebury 
    Original-Tested-by: Vadim Bendebury 
---
 src/mainboard/google/urara/Kconfig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/urara/Kconfig b/src/mainboard/google/urara/Kconfig
index 231c97e..bde26d6 100644
--- a/src/mainboard/google/urara/Kconfig
+++ b/src/mainboard/google/urara/Kconfig
@@ -46,4 +46,8 @@ config DRAM_SIZE_MB
    int
    default 256

+config TTYS0_LCS
+	int
+	default 3
+
 endif