Change in coreboot[master]: soc/intel/alderlake: Enable PCH USB2 Phy power gating

[Sridhar Siricilla (Code Review)]

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63293 )

Change subject: soc/intel/alderlake: Enable PCH USB2 Phy power gating
......................................................................

soc/intel/alderlake: Enable PCH USB2 Phy power gating

The patch adds mechanism in the Alder Lake SoC code to control PCH
USB2 Phy power gating from devicetree.

BUG=b:221461379
TEST=Build and boot Gimble board

Signed-off-by: Sridhar Siricilla 
Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/fsp_params.c
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/63293/1

diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index a69e645..e82f2e4 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -566,6 +566,12 @@
     * Default 0. Set this to 1 in order to disable C state demotion.
     */
    bool disable_c1_state_auto_demotion;
+
+	/*
+	 * Enable PCH USB2 Phy power gating.
+	 * Default 0. Set this to 1 in orderto  disable PCH USB2 Phy Power gating.
+	 */
+	bool usb2_phy_sus_pg_disable;
 };

typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index bd2c0be..5c94f39 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -499,6 +499,8 @@
    	if (config->tcss_ports[i].enable)
    		s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin;
    }
+
+	s_cfg->PmcUsb2PhySusPgEnable = !config->usb2_phy_sus_pg_disable;
 }

static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg,