Attention is currently required from: Raul Rangel, Jon Murphy, Tim Van Patten, Mark Hasemeyer.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74095 )
Change subject: mb/google/myst: First pass GPIO configuration for Myst ......................................................................
Patch Set 8:
(7 comments)
File src/mainboard/google/myst/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/74095/comment/920571b0_114c580d PS8, Line 79: * SPI_SOC_CLK_TCHSCR_R */ SOC_CLK_FPMCU_R since all TS are I2C based for now.
Also these GPIOs should be configured with the NF only when SPI based FPMCU is used. A follow-up bug and a CL is required to address that.
https://review.coreboot.org/c/coreboot/+/74095/comment/34056706_a7fcdc55 PS8, Line 83: /* SPI_SOC_CS_TCHSCR_R_L */ Same comment as in line 79
https://review.coreboot.org/c/coreboot/+/74095/comment/9a0ec35f_d44e2317 PS8, Line 107: SSD WLAN
https://review.coreboot.org/c/coreboot/+/74095/comment/0dcb8984_01b58e29 PS8, Line 109: /* SPI_SOC_DO_TCHSCR_DI_R */ : PAD_NF(GPIO_104, SPI2_DAT0, PULL_NONE), : /* SPI_SOC_DO_TCHSCR_DO_R */ : PAD_NF(GPIO_105, SPI2_DAT1, PULL_NONE) These are FPMCU only for now. Same comment as in line 79.
https://review.coreboot.org/c/coreboot/+/74095/comment/1c3c6544_3bca051d PS8, Line 123: WLAN WWAN
https://review.coreboot.org/c/coreboot/+/74095/comment/dc6b6cc8_cfef5156 PS8, Line 127: / SSD
https://review.coreboot.org/c/coreboot/+/74095/comment/f9d60f1e_0d05f883 PS8, Line 142: PAD_NF(GPIO_140, UART1_TXD, PULL_NONE), Same comment as in line 79
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Karthik Ramasubramanian (Code Review)