Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43173 )
Change subject: nb/intel/gm45: Use ASL 2.0 syntax ......................................................................
nb/intel/gm45: Use ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Ibb9b627de85eb09bdc977af55880366e4e49f3ac Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/gm45/acpi/hostbridge.asl 1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/43173/1
diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index 314908f..6c371cb 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -209,8 +209,8 @@ * Enter actual TOLUD. The TOLUD register contains bits 20-31 of * the top of memory address. */ - ShiftLeft (^MCHC.TLUD, 20, PMIN) - Add(Subtract(PMAX, PMIN), 1, PLEN) + PMIN = ^MCHC.TLUD << 20 + PLEN = PMAX - PMIN + 1
Return (MCRS) }
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43173 )
Change subject: nb/intel/gm45: Use ASL 2.0 syntax ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43173 )
Change subject: nb/intel/gm45: Use ASL 2.0 syntax ......................................................................
nb/intel/gm45: Use ASL 2.0 syntax
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Ibb9b627de85eb09bdc977af55880366e4e49f3ac Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/43173 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: HAOUAS Elyes ehaouas@noos.fr --- M src/northbridge/intel/gm45/acpi/hostbridge.asl 1 file changed, 2 insertions(+), 2 deletions(-)
Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved
diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index d96a7d5..2a8a137 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -208,8 +208,8 @@ * Enter actual TOLUD. The TOLUD register contains bits 20-31 of * the top of memory address. */ - ShiftLeft (^MCHC.TLUD, 20, PMIN) - Add(Subtract(PMAX, PMIN), 1, PLEN) + PMIN = ^MCHC.TLUD << 20 + PLEN = PMAX - PMIN + 1
Return (MCRS) }
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)