Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41664 )
Change subject: AGESA f15tn: Factor out default MTRR settings ......................................................................
AGESA f15tn: Factor out default MTRR settings
All AGESA f15tn boards use the same MTRR values. Factor them out, while still allowing a board to override them via BLDCFG.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries.
Change-Id: I90c95493de1bb5b8f32c06b9575fef3aa7aca031 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/amd/parmer/buildOpts.c M src/mainboard/amd/thatcher/buildOpts.c M src/mainboard/asus/f2a85-m/buildOpts.c M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c M src/mainboard/lenovo/g505s/buildOpts.c M src/mainboard/msi/ms7721/buildOpts.c M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h 7 files changed, 17 insertions(+), 109 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/41664/1
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 05ac8c6..c8af858 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -194,24 +194,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index a97e8f0..c4e0fce 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -194,24 +194,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 8bb0b80..13f2bd8 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -207,24 +207,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 8e90a08..19aac23 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -208,24 +208,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index fd1c977..92a1c69 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -208,24 +208,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index c969d54..c7c4426 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -207,24 +207,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index 4d1ce27..f395fef 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -62,6 +62,22 @@ NULL };
+/* The fixed MTRR values to be set after memory initialization. */ +static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL }, +};
/* Process solution defined socket / family installations * @@ -2433,7 +2449,7 @@ #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) #else - #define CFG_AP_MTRR_SETTINGS_LIST (NULL) + #define CFG_AP_MTRR_SETTINGS_LIST (TrinityApMtrrSettingsList) #endif
#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41664 )
Change subject: AGESA f15tn: Factor out default MTRR settings ......................................................................
Patch Set 1: Code-Review+2
Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41664 )
Change subject: AGESA f15tn: Factor out default MTRR settings ......................................................................
Patch Set 1: Code-Review+1
Hello Mike Banon, build bot (Jenkins), Michał Żygowski, Arthur Heymans, Mike Banon, Krystian Hebel, Alexander Couzens, Patrick Rudolph, Piotr Król,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/41664
to look at the new patch set (#5).
Change subject: AGESA f15tn: Factor out default MTRR settings ......................................................................
AGESA f15tn: Factor out default MTRR settings
All AGESA f15tn boards use the same MTRR values. Factor them out, while still allowing a board to override them via BLDCFG.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries.
Change-Id: I90c95493de1bb5b8f32c06b9575fef3aa7aca031 Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/mainboard/amd/parmer/buildOpts.c M src/mainboard/amd/thatcher/buildOpts.c M src/mainboard/asus/f2a85-m/buildOpts.c M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c M src/mainboard/lenovo/g505s/buildOpts.c M src/mainboard/msi/ms7721/buildOpts.c M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h 7 files changed, 17 insertions(+), 109 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/41664/5
Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41664 )
Change subject: AGESA f15tn: Factor out default MTRR settings ......................................................................
Patch Set 5: Code-Review+2
Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/41664 )
Change subject: AGESA f15tn: Factor out default MTRR settings ......................................................................
AGESA f15tn: Factor out default MTRR settings
All AGESA f15tn boards use the same MTRR values. Factor them out, while still allowing a board to override them via BLDCFG.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb mainboards result in identical coreboot binaries.
Change-Id: I90c95493de1bb5b8f32c06b9575fef3aa7aca031 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/41664 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Mike Banon mikebdp2@gmail.com --- M src/mainboard/amd/parmer/buildOpts.c M src/mainboard/amd/thatcher/buildOpts.c M src/mainboard/asus/f2a85-m/buildOpts.c M src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c M src/mainboard/lenovo/g505s/buildOpts.c M src/mainboard/msi/ms7721/buildOpts.c M src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h 7 files changed, 17 insertions(+), 109 deletions(-)
Approvals: build bot (Jenkins): Verified Mike Banon: Looks good to me, approved
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 05ac8c6..c8af858 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -194,24 +194,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index a97e8f0..c4e0fce 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -194,24 +194,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" #include "cpuFamRegisters.h" diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 8bb0b80..13f2bd8 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -207,24 +207,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 8e90a08..19aac23 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -208,24 +208,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index fd1c977..92a1c69 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -208,24 +208,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index c969d54..c7c4426 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -207,24 +207,6 @@ // #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE // #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
-CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = -{ - { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, - { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, - { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, - { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, - { CPU_LIST_TERMINAL } -}; - -#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList - /* MEMORY_BUS_SPEED */ #define DDR400_FREQUENCY 200 ///< DDR 400 #define DDR533_FREQUENCY 266 ///< DDR 533 diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index d769220..1bca388 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -62,6 +62,22 @@ NULL };
+/* The default fixed MTRR values to be set after memory initialization */ +static const AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = +{ + { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E }, + { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 }, + { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 }, + { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 }, + { CPU_LIST_TERMINAL }, +};
/* Process solution defined socket / family installations * @@ -2425,7 +2441,7 @@ #ifdef BLDCFG_AP_MTRR_SETTINGS_LIST #define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST) #else - #define CFG_AP_MTRR_SETTINGS_LIST (NULL) + #define CFG_AP_MTRR_SETTINGS_LIST (TrinityApMtrrSettingsList) #endif
#ifdef BLDCFG_IOMMU_EXCLUSION_RANGE_LIST
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41664 )
Change subject: AGESA f15tn: Factor out default MTRR settings ......................................................................
Patch Set 6:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4 Emulation targets: "QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/3995 "QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3994 "QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/3993 "QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/3992
Please note: This test is under development and might not be accurate at all!
-
9elements QA (Code Review) -
Angel Pons (Code Review)
-
Arthur Heymans (Code Review)
-
Krystian Hebel (Code Review)
-
Mike Banon (Code Review)
-
Nico Huber (Code Review)